SRAM Write Margin Enhancement via Dynamic Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Static random access memory (SRAM) cells with low static noise margin (SNM) suffer from weak write properties, leading to cell upsets and write failures, especially when scaled down or powered by low supply voltage, due to device mismatch and process variations.
Innovation Solution
A method for writing a memory cell in a specific write cycle involves providing a first signal with a first transition edge and a second signal with a second transition edge, out of phase or lagging behind, to sequentially switch pull-down units and lower the voltage level for reliable data writing, thereby enhancing the write margin and reducing undershoot issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the SRAM cell size is scaled down to increase integration density, then productivity is improved, but manufacturing precision deteriorates due to huge device mismatch from process variation
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the supply voltage to a lowered voltage level during write operations. This voltage adjustment compensates for device mismatch caused by process variation, enabling reliable write operations in scaled-down SRAM cells where transistor parameters vary significantly due to manufacturing tolerances.
2Use of energy by moving object
If the supply voltage is reduced to save power, then use of energy is improved, but reliability deteriorates due to serious write failure from huge device mismatch
Solution Approach 1:
The patent implements dynamics by making the supply voltage time-dependent rather than static. The voltage is dynamically adjusted to a lowered level specifically during write operations when needed, and returned to normal level otherwise. This dynamic voltage adjustment maintains write reliability even at reduced supply voltages, solving the contradiction between power savings and write success rate.
3Use of energy by moving object
If the static noise margin is near zero to minimize voltage levels, then use of energy is improved, but reliability deteriorates due to weak write property causing cell upsets
Solution Approach 1:
The patent applies preliminary action by proactively lowering the supply voltage to a specific lowered voltage level before and during write operations. This preliminary voltage adjustment creates favorable conditions for write operations by reducing the impact of device mismatch, ensuring reliable data writing even when the SRAM cell has minimal static noise margin and operates at near-minimal voltage levels.
Data Source
AI summary
A memory device includes a memory cell electrically connected to a power line and a power supply unit configured to control a voltage level on the power line. The power supply unit receives a control signal corresponding to a write cycle of the memory cell and, responsive to a first state of the control signal, outputs a first voltage level on the power line. Responsive to a second state of the control signal, the power supply unit outputs a second voltage level on the power line, the second voltage level having a magnitude less than a magnitude of the first voltage level.