SRAM ECC Circuit Verification via Error Injection Masking
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Solution Overview
Problem
As SRAMs accommodate more storage elements in a smaller area, they are susceptible to bit errors due to electromagnetic interference, and existing ECC mechanisms face increased error rates, making it challenging to ensure reliable operation.
Innovation Solution
A verifying method for the ECC circuit of SRAM that involves inputting original data into error-correcting-and-coding procedures, injecting errors using a mask, writing and reading data to a test area, and performing bit operations to verify the correctness of the ECC circuit's operation, allowing for both specified and comprehensive bit error checking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage elements are arranged more densely to increase SRAM capacity, then storage capacity per unit area is improved, but susceptibility to bit errors from electromagnetic interference increases
Solution Approach 1:
The verification process is segmented into multiple independent test patterns (e.g., pattern 1 with all 0s, pattern 2 with alternating 0s and 1s, pattern 3 with all 1s). Each pattern targets different aspects of storage element behavior, allowing comprehensive verification without requiring a single complex test that would increase resource usage.
Solution Approach 2:
The verification method changes the data pattern parameters systematically across multiple verification rounds. By varying the input data patterns (all 0s, alternating, all 1s, etc.), the method can detect different types of errors including coupling errors between adjacent storage elements, thereby improving reliability verification without increasing physical density.
2Device complexity
If conventional time-sharing verification methods are used for ECC circuits, then hardware resources are saved, but verification time increases significantly
Solution Approach 1:
The method performs preliminary error injection by XORing the original data with a verification pattern before writing to storage. This preliminary action allows the verification process to detect errors in a single pass rather than requiring multiple time-sharing verification cycles, thereby reducing verification time without adding significant hardware complexity.
Solution Approach 2:
The verification process maintains continuous useful action by integrating error injection and verification operations into a single data flow. Instead of stopping normal operations to perform verification (time-sharing), the method continuously verifies data integrity alongside normal storage operations, reducing the impact on overall system performance.
3Measurement precision
If comprehensive bit error checking is performed across all SRAM areas, then verification completeness is improved, but checking time and hardware costs increase
Solution Approach 1:
The verification method applies different verification patterns to different regions or aspects of the SRAM based on their specific characteristics. For example, it can focus on coupling errors between adjacent elements in high-density regions while using simpler patterns in less critical areas, achieving comprehensive verification without uniformly applying the most rigorous (and time-consuming) checks everywhere.
Solution Approach 2:
The method performs partial verification in the sense that it uses multiple passes with different patterns, where each pass covers specific aspects of error detection. Rather than attempting to detect all possible errors in a single exhaustive pass (which would be overly time-consuming), it uses multiple targeted passes that collectively achieve comprehensive verification efficiency.
Data Source
AI summary
A verifying method for an error checking and correcting (ECC) circuit of a static random-access memory (SRAM) is provided. The SRAM comprises a storage unit, an ECC circuit and a checking circuit. The ECC circuit receives an original data and an output first data. The checking circuit obtains a second data according to an error-injecting mask. The checking circuit performs a bit operation on the first data and the second data to obtain a third data. The checking circuit writes the third data into a test target area of the storage unit and the written data as a fourth data. The checking circuit reads the fourth data from the test target area. The ECC circuit obtains a fifth data and an error message according to the fourth data. The checking circuit obtains the bit error detection result according to the error message and the second data.