Self-Aligned SRAM Edge Resistor Layout for SEU Mitigation
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Solution Overview
Problem
Existing CMOS integrated circuits fabricated in a partially depleted silicon on insulator (SOI) process struggle to mitigate single event upsets (SEUs) caused by radiation in space applications, which can disrupt circuit operation and change the state of memory cells.
Innovation Solution
The method involves fabricating SRAM cells with resistors formed along the sidewall edges of transistors using self-aligned, angled implantation, which enables more compact SRAM architecture and SEU mitigation. This process is done prior to removing the Shallow Trench Isolation (STI) barrier, allowing for precise control over the dimensions and resistance of the self-aligned transistor sidewall edge resistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional resistor designs are used in SRAM cells, then the circuit can operate with standard components, but the area occupied by resistors increases and SEU mitigation is insufficient
Solution Approach 1:
The patent transitions from planar resistor design to three-dimensional sidewall resistor formation. By depositing doped polysilicon on the vertical sidewalls of the transistor structure, the resistor occupies the vertical dimension rather than consuming additional horizontal area, achieving both compactness and high resistance values for SEU mitigation
Solution Approach 2:
The resistor structure is nested within the transistor architecture itself. The doped polysilicon sidewall resistor is formed as an integral part of the transistor structure, utilizing the same fabrication steps and occupying space that would otherwise be empty, thereby eliminating the need for separate resistor components
2Reliability
If high resistance values are achieved using conventional resistors, then SEU mitigation improves, but the resistor area and device complexity increase
Solution Approach 1:
The patent merges the resistor formation process with the existing transistor fabrication sequence. The doped polysilicon sidewall resistor is created using the same polysilicon deposition and doping steps already required for the transistor gates and channels, combining two functions into a single integrated structure
Solution Approach 2:
The sidewall resistor structure serves multiple functions simultaneously: it provides the necessary high resistance for SEU mitigation, defines the transistor active area, and acts as a spacer during fabrication. The structure is self-forming through standard process steps without requiring additional dedicated resistor fabrication equipment or processes
3Area of stationary object
If compact SRAM architecture is implemented, then area efficiency improves, but SEU mitigation capability may be reduced
Solution Approach 1:
The patent applies doping selectively to the sidewall regions rather than uniformly across the entire transistor structure. By confining the doped polysilicon to specific sidewall areas, high resistance is achieved locally where needed for SEU mitigation while maintaining the overall compact transistor dimensions for area efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a compact SRAM architecture with high resistance values (approximately 100,000 to over a million ohms) that effectively reduces or prevents SEUs, suitable for space-based applications across a large temperature range and with low supply voltage.
Implementation Method 1
self-aligned, angled implantation
Data Source
Figure 1~2
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AI summary
This disclosure is directed to techniques for fabricating CMOS devices for SRAM cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well (36) covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator (32) and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby forming a resistor (20) on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type. The method further includes forming a second insulator (50) adjacent to the resistor, removing the barrier, and forming a gate layer (52) on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor.