SRAM End Power Select Circuits for Low-Voltage Write Assist
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Solution Overview
Problem
Static random access memory (SRAM) devices face challenges in reliably writing data at various power supply potentials, necessitating improved reliability over a wide range of operating conditions.
Innovation Solution
The integrated circuit device incorporates end power select circuits with controllable impedance paths and power supply detection circuits to provide write assist, ensuring consistent power supply to SRAM cells even at low voltages, using insulated gate field effect transistors (IGFETs) with vertically aligned channels and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If SRAM devices operate at low power supply potentials, then power consumption is reduced, but data write reliability deteriorates
Solution Approach 1:
The patent applies local quality by providing different power supply potentials to different regions of the SRAM array. Specifically, end power select circuits provide boosted power supply potentials to end rows or columns of the array, while other regions receive the standard low power supply potential. This allows end cells to maintain reliable write operation margins even at low overall operating voltages, while the rest of the array operates efficiently at the lower voltage level.
Solution Approach 2:
The patent implements dynamics through end power select circuits that can dynamically adjust the power supply potential based on operational requirements. These circuits enable or disable additional power delivery to end rows or columns as needed during write operations, allowing the system to adapt the power distribution dynamically rather than using a static power supply configuration throughout the array.
2Loss of energy
If power supply potential is reduced, then energy efficiency improves, but write margin consistency across the array deteriorates
Solution Approach 1:
The patent ensures write margin consistency by providing localized power boosting to specific regions (end rows or columns) where write operations occur. The end power select circuits deliver enhanced power supply potentials to these critical regions, ensuring that write margins remain consistent and sufficient at the ends of the array, while the majority of the array operates at the lower, more energy-efficient power supply potential.
Data Source
AI summary
An integrated circuit device that has improved write margin at low operating voltages is disclosed. The integrated circuit device can include an SRAM array that has end power select circuits that can include selection circuits that provide a controllable impedance path between a power supply potential and an array power line. A power supply detection circuit may provide an assist enable signal when a power supply potential is low enough that write assist is needed. A power control circuit may provide end power control signals to end power select circuits to selectively control an impedance path between a power supply potential and an array power line to provide an I-R drop to a selected memory cell. In this way, write margins may be improved at low operating voltages.