SRAM Cell Equalization Write Assist for Sub-Micron Variability
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Solution Overview
Problem
As semiconductor technology advances, the miniaturization of SRAM cells leads to increased variability in transistor electrical characteristics, causing read and write failures due to the shrinking design window between cell stability and write margin, especially in sub-micron feature sizes, where conventional write-assist techniques are insufficient in maintaining data retention and write accuracy.
Innovation Solution
Incorporating equalization transistors controlled by row and column select signals to short storage nodes during write cycles, assisting in state changes and enhancing write operations without compromising the stability of half-selected cells, thus widening the design window and improving write margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional write-assist techniques are used in miniaturized SRAM cells, then write operations can be performed, but data retention and write accuracy deteriorate due to increased transistor variability in sub-micron feature sizes
Solution Approach 1:
An equalization transistor is introduced as an intermediary component between the two storage nodes in the SRAM cell. This equalization transistor acts as a mediator that selectively equalizes the voltages on the two storage nodes during write operations, thereby improving write accuracy without compromising data retention. The equalization transistor is controlled by control signals that are activated only during write cycles, allowing it to intervene temporarily to assist the write operation while leaving the normal read and hold operations unaffected.
2Area of moving object
If the design window between cell stability and write margin is shrunk to accommodate smaller feature sizes, then memory density increases, but read and write functional failures increase due to transistor variability
Solution Approach 1:
The invention changes the voltage parameters of the storage nodes by introducing an equalization mechanism. During write operations, the equalization transistor temporarily equalizes the voltages on the two storage nodes, effectively changing the voltage state from an asymmetric condition to a symmetric condition. This parameter change assists in overcoming the effects of transistor variability and enables reliable write operations in miniaturized cells where the design window between stability and write margin has been shrunk.
3Reliability
If equalization transistors are added to assist write operations, then write margin improves, but device complexity increases
Solution Approach 1:
The equalization transistor is designed to serve multiple functions: it assists write operations by equalizing storage node voltages, it can potentially assist in correcting certain types of read failures, and it can be used in conjunction with other memory cell designs. By making this additional transistor multi-functional, the penalty of increased device complexity is partially offset by the versatility of the component.
Data Source
AI summary
A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an equalization gate connected between the storage nodes of the storage element. The equalization gate may be realized by two transistors in series, or as a double-gate transistor. The equalization gate is controlled by a word line indicating selection of the row containing the cell in combination with a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to a selected cell, both gates are turned on, connecting the storage nodes of the cell to one another and assisting the write of the opposite date state from that previously stored.