SRAM Cell With Extracted Access Transistor for Leakage Reduction
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Solution Overview
Problem
Traditional SRAM designs face issues with high static power consumption, transistor performance variability leading to memory cell instability and manufacturing yield problems, and increased silicon area due to leakage through access devices and manufacturing process variations.
Innovation Solution
The access transistors are removed from the cell and placed in a separate read-write circuit, with the data storage node connected to the source of an access transistor via a dedicated wire, allowing charge sharing between the data node and the read-write circuit, making the read mechanism independent of access transistor performance and enabling optimization of cell stability and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If access transistors are made strong to enable reliable read/write operations, then data access reliability is improved, but static power consumption increases and cell area increases
Solution Approach 1:
The access transistor is extracted from the traditional 6T cell structure and placed in a separate shared read/write circuit. This allows the cell transistors to be optimized for stability with smaller sizes, while the access function is handled by dedicated transistors in the peripheral circuit that can be stronger when needed, resolving the contradiction between reliable access and low static power consumption.
2Reliability
If access transistors are made strong to ensure reliable data transfer, then data transfer reliability is improved, but manufacturing yield decreases due to transistor performance variability
Solution Approach 1:
By extracting the access transistor from the cell, the design separates the functions of data storage (cell transistors) and data access (access transistor). This allows cell transistors to be smaller and less sensitive to manufacturing variations, improving yield, while the access transistor in the shared circuit can be optimized for reliable data transfer without affecting the cell stability.
3Stability of the object's composition
If cell transistors are made larger to improve cell stability, then cell stability is improved, but silicon area increases
Solution Approach 1:
The access transistor is taken out from the cell structure, allowing cell transistors to be optimized purely for stability without needing to be oversized for access functions. The access function is handled by the separate access transistor in the read/write circuit, enabling smaller cell area while maintaining stability.
4Adaptability or versatility
If access transistors are included in the cell to enable read/write operations, then data access functionality is improved, but leakage current increases
Solution Approach 1:
The access transistor is extracted from the cell and placed in a shared read/write circuit. This eliminates the leakage path through access transistors from each cell, as the shared circuit only activates one access transistor at a time during read/write operations, significantly reducing standby leakage current while maintaining full data access functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption, improves cell stability, and increases manufacturing yield by eliminating the need for strong access transistors, allowing for weaker cell transistors and reduced leakage, while maintaining reliable data transfer and storage.
Implementation Method 1
Enabling the access transistor causes charge sharing between the data node and the rw_data node. Because the data node capacitance is much greater that the rw_data node capacitance the voltage present on the data node dominates thereby reading the data contents of the cell.
Data Source
AI summary
The present application relates to an improved static random access memory (SRAM) device having a plurality of storage cells and a separate read/write circuit. Each of the plurality of storage cells is connected to a read/write data node of the read/write circuit by a dedicated connection, and an access switch which permits read/write access to the storage cell. The dedicated connection exhibits a greater capacitance than the read/write data node of the read/write circuit, such that the primary read mechanism of the SRAM is charge equalization. The SRAM write data connection to the read/write node of the read/write circuit, to permit data to be written to the plurality of storage cells. Write assist techniques are disclosed which assist writing of a ‘1’ to the plurality of storage cells.