SRAM Memory Cell With Dynamic Feedback Interrupt for Read Disturb
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Solution Overview
Problem
Static random-access memory (SRAM) cells suffer from read disturb bumps and write failures due to voltage dividers and cross-coupled inverter contention, which become more pronounced at smaller fabrication scales and lower operating voltages, limiting minimum voltage operation and reliability.
Innovation Solution
Implementing a memory cell with dynamic disturb reduction (DDR) that includes a broken feedback write circuit and buffered read circuitry, using a 10-transistor configuration with dynamic disturb reduction (DDR) to isolate nodes from voltage bumps and reduce transistor count, area, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM cell design is used, then device complexity is low, but read reliability deteriorates due to read disturb bumps
Solution Approach 1:
The patent introduces an interrupt circuit as an intermediary component that disables the feedback path of the first inverter during read operations. This mediator prevents the propagation of read disturb bumps through the cross-coupled inverter, thereby improving read reliability without requiring complete redesign of the SRAM cell structure.
Solution Approach 2:
The patent segments the SRAM cell operations into distinct read and write modes by using wordline signals to control the interrupt circuit. During read operations, the interrupt circuit is activated to isolate the feedback path, while during write operations, the feedback path is restored. This segmentation allows the cell to optimize for different operational modes independently.
2Reliability
If conventional SRAM cell design is used, then device complexity is low, but write reliability deteriorates due to write failures from inverter contention
Solution Approach 1:
The patent makes the feedback path dynamic by using the interrupt circuit controlled by wordline signals. During write operations, the interrupt circuit disables the feedback path to eliminate inverter contention, while during read operations, the feedback path is re-enabled. This dynamic control allows the cell to adapt its behavior based on the current operation mode, improving write reliability without permanent structural changes.
3Reliability
If operations are performed at lower voltages, then energy consumption decreases, but reliability deteriorates due to pronounced read disturb bumps and write failures
Solution Approach 1:
The patent applies preliminary anti-action by preemptively disabling the feedback path during read operations before read disturb bumps can cause state flips. The interrupt circuit is activated in anticipation of the read operation, preventing the harmful feedback effect from occurring in the first place, thereby maintaining reliability at lower voltages where disturb bumps are more pronounced.
4Reliability
If additional circuitry is added to reduce disturb bumps, then reliability improves, but area increases
Solution Approach 1:
The interrupt circuit serves multiple functions: it disables feedback during read operations to prevent read disturb bumps, and disables feedback during write operations to prevent write contention. This multi-functionality allows a single additional component to address both read and write reliability issues simultaneously, minimizing the area increase compared to separate solutions for each problem.
Data Source
AI summary
A memory cell with dynamic disturb reduction includes first and second inverters in a cross-coupled arrangement, a write circuit to write to the memory cell, a read circuit to read the memory cell, and an interrupt circuit to disable at least a portion of the first inverter when the read circuit reads the memory cell.