SRAM FinFET with Variable Height Fins for Layout Optimization
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Solution Overview
Problem
Conventional FinFETs present design challenges in achieving the required on-current and off-current ratios for high-performance SRAM cells, as they have fixed fin heights, limiting the flexibility to adjust transistor widths and resulting in increased layout area or reduced on-current when attempting to maintain optimal current ratios.
Innovation Solution
The SRAM cell design allows for FinFETs with fins of different heights by using a semiconductor layer comprising multiple sub-layers with etching selectivity, enabling precise control and patterning of fin heights to achieve varying channel widths and current ratios without increasing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional FinFETs with fixed fin heights are used, then lithographic patterning is facilitated, but the flexibility to adjust transistor widths and achieve optimal current ratios is limited
Solution Approach 1:
The semiconductor layer is divided into multiple sub-layers with different etching selectivities. By selectively etching different numbers of sub-layers, fins of different heights are created for different transistors, enabling independent width adjustment while maintaining lithographic patterning benefits
Solution Approach 2:
Different regions of the semiconductor layer are structured with different numbers of sub-layers, creating local variations in fin height. This allows each transistor to have optimized fin height and channel width according to its specific current requirements, while the overall structure remains manufacturable
2Manufacturing precision
If fins of different heights are created to achieve optimal current ratios, then transistor current control is improved, but manufacturing complexity increases
Solution Approach 1:
The fin height parameter is controlled by varying the number of semiconductor sub-layers etched in different regions. This provides precise control over fin height and channel width through material layering rather than complex patterning processes
Solution Approach 2:
Multiple semiconductor sub-layers with different etching selectivities act as intermediaries between the lithographic patterning step and the final fin structure. These sub-layers enable precise fin height control without requiring additional complex patterning steps
3Adaptability or versatility
If conventional MOSFETs are used instead of FinFETs, then device width can be freely adjusted, but switching speed and current density are reduced
Solution Approach 1:
The invention transitions from planar MOSFETs to vertical FinFETs, adding the vertical dimension through fin structures. The multiple sub-layer approach then provides additional control in the vertical dimension, enabling both high switching speed from the fin structure and adjustable effective width through selective etching
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient manufacturing of SRAM cells with FinFETs having different fin heights, enabling optimal current ratios and reducing layout area, thereby improving the performance and efficiency of SRAM cells.
Implementation Method 1
The semiconductor layer comprises a plurality of semiconductor sub-layers. The first and second fins comprise different number of the semiconductor sub-layers and thus have different heights from each other
Data Source
AI summary
In one embodiment, a SRAM cell may include a substrate and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the substrate. The first FinFET may include a first fin which is formed in a semiconductor layer provided on the substrate and abuts the semiconductor layer, and the second FinFET may include a second fin which is formed in the semiconductor layer and abuts the semiconductor layer. The semiconductor layer may include a plurality of semiconductor sub-layers. The first and second fins can include different number of the semiconductor sub-layers and have different heights from each other.