SRAM Cell Fin-Transistor Parasitic Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Fin-type transistors in SRAM cells exhibit higher parasitic capacitance due to their three-dimensional structure, leading to increased risk of insufficient access performance and higher power consumption.
Innovation Solution
Incorporating a thinner local metal interconnection layer below the first metal interconnection layer, with diffusion and gate contacts formed on a contact layer, and bit lines formed on the local metal interconnection layer, reducing parasitic capacitance by simplifying the signal path from pass gate transistors to bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a fin-type transistor with three-dimensional structure is used, then channel controllability and ON-state current are improved, but parasitic capacitance increases
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a three-dimensional fin-type structure with vertical channels. This dimensional change increases the effective channel area and improves controllability while managing the associated parasitic capacitance through optimized gate wrapping geometry and interconnection layer design.
2Adaptability or versatility
If bit lines are formed on a second metal interconnection layer, then routing flexibility is improved, but parasitic capacitance of the bit line increases due to longer signal paths through multiple interconnection layers
Solution Approach 1:
The patent segments the interconnection structure into multiple layers with specific functions. The local metal interconnection layer is dedicated to bit line formation, while other metal layers handle different routing functions. This segmentation allows bit lines to be formed on an intermediate layer, reducing the number of via layers signals must traverse and thereby reducing parasitic capacitance.
Solution Approach 2:
The patent introduces a local metal interconnection layer as an intermediary between the first and second metal interconnection layers. This intermediate layer serves as a dedicated pathway for bit lines, reducing the signal path length and parasitic capacitance compared to forming bit lines directly on the second metal layer, while still maintaining routing flexibility.
Data Source
AI summary
The present disclosure allows for reducing parasitic capacitance of a bit line, and a drop in access performance in an SRAM cell including fin-type transistors. The SRAM cell is defined by transistors each of which has a fin structure and by a local metal interconnection layer. Bit lines are formed on the local metal interconnection layer, and diffusion layer contacts corresponding to bit line nodes are connected through vias to the bit lines.