SRAM FinFET Layout With Shared SOI Regions for Simpler Fabrication
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Solution Overview
Problem
Conventional finFET fabrication methods require a large number of processing steps and may not scale well to smaller feature sizes, leading to increased fabrication costs and reduced yields.
Innovation Solution
A semiconductor fabrication method that includes doping portions of a silicon-on-insulator (SOI) substrate corresponding to doped regions of a finFET and a via contact in a single processing step, followed by gate formation, which reduces the number of processing steps and facilitates scaling to smaller feature sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional finFET fabrication methods are used with multiple processing steps, then manufacturing precision can be maintained, but device complexity and fabrication cost increase
Solution Approach 1:
The patent combines multiple separate fabrication steps into a single integrated process. Specifically, the method forms the fin structure, performs doping, and creates isolation regions simultaneously in one processing step, rather than executing these as separate sequential operations. This merging reduces process complexity while maintaining the precision needed for finFET fabrication at small feature sizes
Solution Approach 2:
The fabrication method employs a universal process that accomplishes multiple functions in a single step. The same processing step that forms the fin structure also performs the doping and creates the isolation regions, making the process multi-functional. This universality reduces the total number of steps required while maintaining manufacturing precision for all three functions
2Manufacturing precision
If conventional finFET fabrication methods with multiple processing steps are used, then manufacturing precision can be maintained, but productivity decreases
Solution Approach 1:
By merging the formation of fin structures, doping, and isolation region creation into a single processing step, the patent significantly reduces the total fabrication time. This consolidation eliminates the need for multiple sequential operations, thereby increasing productivity and fabrication throughput while maintaining the precision required for small feature size finFETs
3Length of moving object
If feature sizes are reduced in conventional finFET fabrication, then device scaling is achieved, but manufacturing precision and yield decrease
Solution Approach 1:
The patent's integrated fabrication method forms fin structures, performs doping, and creates isolation regions simultaneously in one step, which is particularly advantageous for small feature sizes. This approach maintains manufacturing precision at reduced feature dimensions by avoiding multiple alignment steps that would compound errors and reduce yield in conventional multi-step processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the finFET fabrication process, potentially increasing yields and reducing fabrication expenses while enabling the production of finFETs with smaller feature sizes.
Implementation Method 1
forming a fully-depleted channel of a finFET in a cell of a static random-access memory (SRAM) by doping, in a same processing step, portions of a silicon-on-insulator (SOI) substrate of an integrated circuit
Data Source
AI summary
Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.