SRAM Double-Edge Flip-Flop Layout for Lower Power and Area
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Solution Overview
Problem
Double edge triggered flip-flop circuits face challenges in reducing power consumption and circuit area due to the need for multiple latch circuits and transistors, which increases power for clock signal charging and discharging, and occupies more space.
Innovation Solution
A flip-flop circuit configuration with a first latch circuit latching data at either the rising or falling edge of a clock signal and a second latch circuit in parallel, where at least one of the latch circuits is SRAM type, and sharing inverters to reduce the number of transistors and circuit area, while maintaining operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a double edge triggered flip-flop circuit uses two latch circuits arranged in parallel, then the operation speed is improved (same speed at half clock frequency), but the power consumption increases due to more transistors turning on and off by the clock signal
Solution Approach 1:
The circuit is divided into two separate latch circuits, each handling different clock edges (rising and falling). This segmentation allows each latch to operate independently with fewer transistors, reducing the total power consumption while maintaining the double-edge-triggered functionality and operation speed.
Solution Approach 2:
The invention changes the transistor count parameter by using optimized latch circuit designs that require fewer transistors per latch. By reducing the transistor count in each latch circuit, the total power consumption for charging and discharging capacitances is reduced while still achieving double-edge triggering capability.
2Speed
If two latch circuits are provided in parallel for double edge triggering, then the clock frequency can be halved, but the circuit area increases
Solution Approach 1:
The two latch circuits are merged into a unified structure where they share common components and are integrated in a compact arrangement. This merging approach reduces the total circuit area compared to having two completely separate latch circuits, while still maintaining the parallel operation needed for double-edge triggering at half the clock frequency.
3Use of energy by stationary object
If multiple latch circuits are used for double edge triggering, then power consumption is reduced at half clock frequency, but the number of transistors increases requiring more power for charging and discharging
Solution Approach 1:
The invention optimizes the transistor count parameter in each latch circuit by using efficient circuit designs. By changing the transistor configuration and reducing redundant transistors, the total number of transistors is minimized, which directly reduces the power required for charging and discharging transistor capacitances while maintaining the power-saving benefit of half-clock-frequency operation.
Data Source
AI summary
In a double edge triggered flip-flop circuit, a first latch circuit latches input data at either one of rising edge and falling edge of clock signal. A second latch circuit, which is provided in parallel with the first latch circuit, latches the input data at the other of the either one of rising edge and falling edge of the clock signal. At least one of the first latch circuit and the second latch circuit is configured by an SRAM (Static Random Access Memory) type.