SRAM Nanosheet Layout Using Floating Sheets for Read-Write Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor structures for SRAM fail to achieve optimal reading and writing margins without increasing area, as they rely on large width nanosheets for driver strength, leading to an area penalty, and existing methods using different fin lengths for transistors do not effectively scale for improved program margin.
Innovation Solution
The use of multiple transistors with varying numbers of active and floating nanosheets, where active sheets are connected between source and drain and biased by external voltage, and floating sheets are isolated, allowing for different relative strengths without increasing nanosheet width, thereby improving sensing and program margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the nanosheet width is increased to improve drive current, then the reading and writing margins are improved, but the device area increases
Solution Approach 1:
The patent segments the nanosheet channel into multiple discrete sheets (first sheet, second sheet, third sheet) with different widths. Each sheet contributes differently to the drive current, allowing the transistor to achieve high drive current through the combined effect of multiple narrower sheets rather than relying on a single wide sheet. This segmentation enables improved reading and writing margins while maintaining a compact device area.
Solution Approach 2:
The patent applies local quality by assigning different widths to different nanosheet segments within the same transistor channel. The first nanosheet has a first width, the second nanosheet has a second width, and the third nanosheet has a third width, creating local variations in current contribution. This allows optimization of drive current distribution across the channel while maintaining overall device compactness.
2Measurement precision
If high bitline strength is increased to improve reading margin, then the reading sensitivity is improved, but the inverter overpowering during reads increases
Solution Approach 1:
The patent creates dynamically adjustable drive strengths for different transistors within the SRAM cell by configuring different numbers and widths of nanosheets in each transistor. The access transistors, pull-up transistors, and pull-down transistors can be independently optimized with different nanosheet configurations, allowing the circuit to dynamically balance reading and writing operations without fixed overpowering issues.
Data Source
AI summary
An integrated circuit structure includes a memory cell and multiple transistors therein. The multiple transistors are formed using channels including a stack having alternating layers of conductive semiconductor material and layers of other material that are insulative. Two or more of the multiple transistors have a same number of layers of the conductive semiconductor material in corresponding channel regions but have different numbers of active layers and inactive layers of the conductive semiconductor material. An active layer is a layer forming a channel in the channel region that is electrically coupled to S/D regions in a corresponding transistor, while a floating layer is a layer in the channel region electrically isolated from the S/D regions in the corresponding transistor. Methods for forming the integrated circuit structure are disclosed.