SRAM GAA Transistor Layout with Fewer P-Channel Layers
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Solution Overview
Problem
SRAM chips with GAA transistors face reduced read and write margins due to high current levels in p-type transistors, which are detrimental to optimal performance, and existing methods struggle to balance current levels between n-type and p-type transistors without sacrificing fin dimensions or increasing processing costs.
Innovation Solution
The approach involves configuring SRAM cells with p-type GAA transistors having a reduced number of channel layers compared to n-type GAA transistors, allowing for smaller epitaxial source/drain features and improved current balance by maintaining different lateral widths for base fins, thereby reducing current levels in p-type transistors and enhancing read/write margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If p-type GAA transistors use the same number of channel layers as n-type GAA transistors, then device symmetry is maintained, but current balance between n-type and p-type transistors deteriorates leading to reduced read and write margins
Solution Approach 1:
The patent applies asymmetry by configuring p-type GAA transistors with a reduced number of channel layers compared to n-type GAA transistors. Specifically, n-type transistors have a first number of channel layers while p-type transistors have a second number of channel layers that is less than the first number. This asymmetric configuration balances the current levels between n-type and p-type transistors, improving read and write margins without requiring complex additional structures.
Solution Approach 2:
The patent implements local quality by applying different channel layer configurations to different transistor types within the same SRAM cell. The n-type transistors maintain a standard number of channel layers for optimal electron transport, while p-type transistors use reduced channel layers to compensate for higher hole mobility. This localized differentiation optimizes current balance specifically where needed without affecting other device characteristics.
2Power
If epitaxial source/drain features are made larger to improve transistor performance, then current drive increases, but leakage between adjacent features increases
Solution Approach 1:
The patent converts the potential harm of large epitaxial source/drain features causing leakage into a benefit by strategically positioning them. The method forms epitaxial source/drain features that extend into regions between adjacent fin structures, but controls their positioning and dimensions so they provide beneficial current drive while the reduced channel layers in p-type transistors compensate for any residual leakage effects.
Solution Approach 2:
The patent applies parameter changes by adjusting the dimensions and positioning of epitaxial source/drain features. The features are configured to have specific lateral widths and extension lengths that optimize current drive capability. By changing these geometric parameters and combining them with asymmetric channel layer configurations, the patent achieves high current drive while maintaining acceptable leakage levels.
Data Source
AI summary
A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.