SRAM Gate-Channel Doping to Reduce Threshold Voltage Anti-Correlation
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Solution Overview
Problem
The challenge in designing Static Random-Access Memory (SRAM) is to achieve a lower minimum operating voltage (Vmin) while addressing the issue of threshold voltage anti-correlation between N-type and P-type transistors, which degrades the minimum operating voltage of SRAM.
Innovation Solution
Incorporating a dipole material or halogen (such as fluorine) in the gate-channel arrangements of some or all transistors of one type, but excluding these materials in the gate-channel arrangements of all transistors of the other type, to alter the correlation between the threshold voltages of N-type and P-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dipole material or halogen is used to alter threshold voltage correlation, then minimum operating voltage is improved, but the device complexity increases due to selective material incorporation
Solution Approach 1:
The patent segments the transistor population into two distinct groups: N-type transistors (or P-type) that contain dipole material or halogen, and the other type that does not. This segmentation allows independent optimization of threshold voltages for each transistor type, achieving lower minimum operating voltage while managing complexity through clear differentiation of transistor characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved minimum operating voltage of SRAM by reducing or eliminating threshold voltage anti-correlation, enabling the use of a wider array of gate electrode materials while maintaining desirable gate control.
Implementation Method 1
Incorporating a dipole material or halogen (such as fluorine) in the gate-channel arrangements of some or all transistors of one type
Implementation Method 2
alter the correlation between the threshold voltages of N-type and P-type transistors
Data Source
AI summary
Disclosed herein are IC structures with transistor gate-channel arrangements for SRAM, and related methods and devices. Example IC structure may include a memory cell with a plurality of transistors including transistors of a first type and transistors of a second type (e.g., the first type may be an N-type and the second type may be a P-type, or vice versa), an individual transistor comprising a transistor gate-channel arrangement that includes a channel material and a transistor gate stack, and the transistor gate stack comprising a gate electrode material and a high-k dielectric between the gate electrode material and the channel material. The transistor gate-channel arrangement of at least one transistor of the first type further includes a dipole material or a halogen (e.g., fluorine), which are absent in the transistor gate-channel arrangements of all of the transistors of the second type.