SRAM Cell Gate Line Segmentation for Charge Accumulation
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Solution Overview
Problem
The 6T SRAM device experiences instability and leakage current due to charge accumulation at the edge transistors, particularly on silicon on insulator (SOI) substrates, which affects the threshold voltage and overall performance.
Innovation Solution
The design incorporates L-like shaped gate lines and gated diodes to reduce charge accumulation at the edge regions of the SRAM cell array, with heavily doped regions and a gate insulating layer to manage substrate voltages and improve transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple P-well lines and N-well lines are formed in long line shape by interleaving in the substrate, then the SRAM cell structure can be implemented, but charge accumulation occurs at the far end transistors causing threshold voltage decrease and performance degradation
Solution Approach 1:
The long P-well line and N-well line are divided into multiple segments by inserting well isolation lines between them. This segmentation prevents charge accumulation by electrically isolating different sections of the well lines, thereby maintaining stable threshold voltage across all transistors in the SRAM cell array while preserving the interleaved structure implementation.
2Ease of manufacture
If substrate voltage is applied from an end terminal to the whole well line, then the well line can be formed, but the transistors at the far end accumulate charges causing leakage current and instability
Solution Approach 1:
The well line is segmented into multiple isolated sections using well isolation lines. Each segment can be independently voltage-controlled, preventing charge accumulation along the entire line. This segmentation eliminates the harmful charge buildup at far-end transistors while maintaining the ability to form complete well lines for transistor operation.
3Device complexity
If the gate lines are formed in straight lines connecting transistors, then the circuit layout is simple, but charge accumulation occurs at edge regions affecting threshold voltage
Solution Approach 1:
The gate lines are designed with L-like shapes that create bending portions at strategic locations. These bends act as charge accumulation relief points, segmenting the charge distribution along the gate line. This geometric modification prevents harmful charge buildup at edge regions while maintaining relatively simple circuit connectivity.
Data Source
AI summary
A semiconductor device has a 6T SRAM cell formed on a substrate. The SRAM cell includes a first and a second PMOS transistors formed over an N-well line in a substrate. A first and a second NMOS transistors are formed over a first P-well line in the substrate at a first side of the N-well line. A third and a fourth NMOS transistors are formed over a second P-well line in the substrate at a second side of the N-well line. A first gate line connects gates of the first PMOS transistor and the first NMOS transistor. A second gate line connects a gate of the second NMOS transistor. A third gate line connects gates of the second PMOS transistor and the third NMOS transistor. A fourth gate line connects a gate of the fourth NMOS transistor. The first gate line and the third gate line are in L-shape.