SRAM Memory Cell Using Gate Oxide Charge Storage
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Solution Overview
Problem
Existing semiconductor memory devices face issues with charge retention characteristics and reliability due to thick gate insulating films, increased transistor count, complex peripheral circuits, low write efficiency, and additional costs associated with deep n-well formation.
Innovation Solution
A semiconductor memory device with SRAM cells using PMOS and NMOS transistors on n-type and p-type wells, respectively, where electrons are accumulated in gate insulating films instead of a floating gate, using the drain avalanche hot electron injection theory, eliminating the need for negative voltages and allowing for thin gate insulating films without modifying the CMOS process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a floating gate is used in the storage node, then write operations can be performed through drain avalanche hot electron injection, but the gate insulating film must be thick (8-9 nm or more) to prevent charge loss, which causes the charges retention characteristic to deteriorate and reliability to decrease
Solution Approach 1:
The patent removes the floating gate structure from the memory cell, extracting the problematic charge storage mechanism that required thick gate insulating films. By eliminating the floating gate, the invention avoids the need for thick insulating films while maintaining charge retention capability through alternative mechanisms in the gate oxide film.
Solution Approach 2:
The patent changes the operating parameters and physical state of the gate oxide film by applying positive voltage during write operations to enable hot electron injection into the gate oxide film. This parameter change allows thin gate insulating films to function effectively without the charge loss problems of conventional floating gate structures.
2Measurement precision
If two n-channel MISFETs and a p-channel MISFET are included in each memory cell, then read operations can be performed by sensing current difference, but the transistor count increases and the area of the memory cell increases
Solution Approach 1:
The patent makes the gate oxide film serve multiple functions: it acts as both the insulating layer and the charge storage medium, and the same structure is used for both read and write operations. This multi-functionality eliminates the need for separate floating gates and complex transistor configurations, reducing memory cell area while maintaining sensing capability.
Solution Approach 2:
The patent merges the gate oxide film with the charge storage function, combining what were previously separate components (gate insulating film and floating gate) into a single integrated structure that performs both insulation and charge storage functions simultaneously.
3Reliability
If substrate hot hole injection is used to inject charges into gate oxide film and oxide film side spacer, then write operations can be performed, but negative voltage is required which complicates peripheral circuits and reduces write efficiency
Solution Approach 1:
The patent inverts the conventional approach by using positive voltage instead of negative voltage to drive hot electron injection into the gate oxide film. This inversion simplifies the peripheral circuits by eliminating the need for negative voltage generation while maintaining effective charge injection capability.
Solution Approach 2:
The patent changes the voltage parameter from negative to positive, fundamentally altering the injection mechanism from substrate hot hole injection to drain avalanche hot electron injection. This parameter change simplifies peripheral circuits and improves write efficiency by eliminating complex negative voltage requirements.
4Reliability
If deep n-well formation is added to CMOS process, then substrate hot hole injection can be performed, but additional costs are incurred
Solution Approach 1:
The patent extracts and eliminates the need for deep n-well formation by using positive voltage-driven hot electron injection into the existing gate oxide film. This removes the additional manufacturing step and associated costs while maintaining write operation capability.
Solution Approach 2:
The patent uses the existing gate oxide film as the charge storage medium, replacing the need for expensive deep n-well formation. The gate oxide film serves as a disposable-like component that is already present in standard CMOS processes, eliminating additional manufacturing costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a highly reliable memory device with improved retention characteristics, simplified peripheral circuits, and increased write efficiency, enabling high write rates without the need for negative voltages or additional processing steps.
Implementation Method 1
Writing to this type of memory cell is performed through drain avalanche hot electron injection into the floating gate in the storage node
Implementation Method 2
Hot holes 472 injected from the p-type silicon substrate 461 to the n-type well 463 are accelerated toward a vicinity of the source 469. By use of the substrate hot hole theory, trap holes 473 are injected into the gate oxide film 465 and the oxide film side spacer 468 near the source
Data Source
AI summary
Obtained is a highly-reliable non-volatile memory without increasing the area of a memory cell or adding a step to a CMOS process. The non-volatile memory includes an SRAM cell configured of 6 MOS transistors, a first word line electrically connected to the gate of a first transfer MOS transistor, and a second word line electrically connected to the gate of a second transfer MOS transistor. During a write operation of a first PMOS transistor, a drive circuit applies a positive voltage whose absolute value is not larger than a junction breakdown voltage to an n-type well as well as the sources of first and second PMOS transistors, concurrently applying the positive voltage to the first word line and a ground voltage to the second word line and a first data line.