SRAM Gate Resistance Reduction via Selective Silicide Junctions
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Solution Overview
Problem
In integrated circuit designs, particularly for SRAM cells, the use of self-aligned contacts and silicide structures is mutually exclusive, leading to high gate resistance due to the cap layer preventing silicide formation on poly gates, which hinders proper circuit function.
Innovation Solution
A semiconductor structure is developed with a gate layer doped with impurities of different types, featuring a cap layer with openings at junctions to allow silicide formation, reducing resistance between gate portions and enabling simultaneous self-aligned silicide and contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cap layer is formed on the poly gate to enable self-aligned contacts, then the poly gate is protected from silicide formation, but the gate resistance becomes too high for proper circuit function
Solution Approach 1:
The gate layer is divided into two portions with different doping types (first type and second type impurities). The cap layer is selectively removed at the junction between these portions, allowing silicide formation only in that specific region. This segmentation enables the gate to have both protection (where cap layer remains) and low resistance (where silicide forms).
Solution Approach 2:
Different regions of the gate structure are given different properties: the majority of the gate retains the cap layer for protection and proper alignment, while the junction region has the cap layer removed to allow silicide formation and reduce resistance. This local differentiation resolves the contradiction between overall protection and localized conductivity needs.
2Ease of manufacture
If self-aligned contact structure is used with cap layer, then via formation is facilitated, but silicide formation on poly gate is prevented leading to high resistance
Solution Approach 1:
The gate layer is pre-doped with different types of impurities in different portions before the cap layer is applied. This preliminary differentiation of doping types allows subsequent selective silicide formation at the junction when the cap layer is locally removed, while maintaining the self-aligned contact structure for easy via formation.
3Ease of manufacture
If the gate layer is uniformly doped, then manufacturing is simplified, but resistance at the junction between differently doped regions cannot be reduced
Solution Approach 1:
The gate layer is doped with different types of impurities (first type in one portion, second type in another portion) to create local electrical property differences. This local doping differentiation enables subsequent selective silicide formation at the junction region to reduce resistance, while maintaining relatively simple overall manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate resistance by forming silicide contacts at the junctions of differently doped gate portions, allowing for effective electrical connections while maintaining self-aligned contacts, thereby enhancing circuit performance.
Implementation Method 1
A silicide layer is formed on the gate layer that is exposed by the opening for reducing resistance at the junction between the first and second portions of the gate silicon layer
Implementation Method 2
A cap layer is formed on the gate layer for protecting the same covered thereunder from forming a silicide structure
Implementation Method 3
a first portion of the gate layer running across the first device area is doped with impurities of a first type, and a second portion of the gate layer running across the second device area is doped with impurities of a second type
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate having a first device area and a second device area. A gate layer is formed across the first device area and the second device area on the semiconductor substrate, wherein a first portion of the gate layer running across the first device area is doped with impurities of a type different from that of a second portion of the gate layer running across the second device area. A cap layer is formed on the gate layer for protecting the same covered thereunder from forming a silicide structure, having at least one opening at a junction of the first and second portions of the gate layer. A silicide layer is formed on the gate layer that is exposed by the opening for reducing resistance at the junction between the first and second portions.