SRAM Global Bitline Circuits Reducing Power Glitches
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Solution Overview
Problem
The use of global bitlines in SRAM can result in power glitches during memory read operations due to timing characteristics, leading to increased power consumption, and delaying data transfer to avoid glitches increases memory read access latency.
Innovation Solution
Implementing a global bitline enable generation circuit that triggers data transfer from an aggregated read bitline to a global bitline based on a falling transition of the system clock, rather than a rising transition, to reduce or avoid power glitches without increasing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data transfer from aggregated read bitline to global bitline is triggered by rising transition of system clock, then data transfer timing is simplified, but power glitches occur during memory read operations
Solution Approach 1:
The patent inverts the conventional approach by triggering data transfer on the falling transition of the system clock instead of the rising transition. This inversion changes the timing relationship between the clock signal and the data transfer operation, allowing the transfer to occur after the clock has already transitioned high, thereby avoiding the power glitch condition that occurs with rising-edge triggering while maintaining simplified control logic.
2Loss of energy
If data transfer is delayed to avoid power glitches, then power consumption is reduced, but memory read access latency increases
Solution Approach 1:
The patent performs preliminary action by pre-charging the global bitline during the period when the clock is high, before the actual data transfer occurs. This pre-charging prepares the bitline in advance so that when data transfer happens on the falling edge, the glitch-prone transition period has already passed, thereby avoiding the need to delay data transfer and preventing increased latency.
3Loss of energy
If global bitline is pre-charged earlier, then power glitches are avoided, but the control circuit complexity increases
Solution Approach 1:
The patent makes the control circuit multi-functional by using the same clock signal to serve dual purposes: first as the trigger for pre-charging the global bitline, and then as the trigger for data transfer on its falling edge. This eliminates the need for separate control signals or additional circuitry, achieving power glitch reduction without increasing control circuit complexity.
Data Source
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AI summary
Static random access memory (SRAM) global bitline circuits for reducing glitches during read accesses, and related methods and systems are disclosed. A global bitline scheme in SRAM can reduce output load, reducing power consumption. In certain embodiments, SRAM includes an SRAM array. The SRAM includes a global bitline circuit for each SRAM array column. Each global bitline circuit includes memory access circuit that pre-charges local bitlines corresponding to bitcells in SRAM array. The data read from selected bitcell is read from its local bitline onto aggregated read bitline, an aggregation of local bitlines. The SRAM includes bitline evaluation circuit that sends data from aggregated read bitline onto global bitline. Instead of sending data based on rising transition of clock trigger, data is sent onto the global bitline based on falling transition of clock trigger. A global bitline scheme can be employed that reduces glitches and resulting increases in power consumption.