SRAM Bit-Cell Reset Before Write Architecture
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Solution Overview
Problem
SRAMs face challenges in low voltage operation regarding write ability, stability during read, and retention, particularly in half-selected bit-cells, where improving write ability degrades stability and vice versa, especially at lower supply voltages.
Innovation Solution
The proposed SRAM bit-cell architecture incorporates a separate read port with a feedback mechanism that ensures stability by writing original data back to half-selected bit-cells through their write bit-lines, maintaining data integrity and allowing 100% write ability without new data being written to half-selected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the write ability of SRAM cell is improved by adjusting pass-gate current strength, then write ability is improved, but stability of half-selected bit-cells is degraded
Solution Approach 1:
The patent applies preliminary action by resetting the write bit-line to match the stored data value before the write operation begins. This is achieved by using a separate read port to detect the stored data and conditionally reset the write bit-line during the write setup phase. By preparing the write bit-line in advance to hold the correct data value, the patent ensures that half-selected bit-cells are protected from unwanted writes while the selected bit-cell can be properly written, thus resolving the contradiction between write ability and stability.
Solution Approach 2:
The patent employs feedback by using a separate read port to detect the stored data value in half-selected bit-cells and using this information to control the reset of the write bit-line. The read port provides feedback about the current state of the bit-cell, which is then used to adjust the write bit-line voltage appropriately. This feedback mechanism ensures that the write operation only affects the intended selected bit-cell while maintaining stability in half-selected bit-cells, thereby resolving the write ability versus stability contradiction.
2Use of energy by moving object
If NMOS pass-gate current strength is increased to write at lower supply voltages, then write ability at low voltage is improved, but power consumption and variability increase
Solution Approach 1:
The patent applies preliminary action by resetting the write bit-line to the correct data value before the actual write operation. This preparation step ensures that the write bit-line is already at the appropriate voltage level, reducing the burden on the pass-gate during the write operation. By pre-positioning the write bit-line voltage, the patent enables reliable writing at lower supply voltages without requiring excessive pass-gate current strength, thus improving low-voltage write ability while reducing variability.
Solution Approach 2:
The patent introduces an intermediary mechanism - the separate read port and associated control logic - that mediates between the stored data and the write bit-line. This intermediary detects the stored data value and uses it to conditionally reset the write bit-line, creating a buffer that stabilizes the write operation. This intermediary structure enables more predictable write behavior at lower voltages by reducing direct dependence on pass-gate current variability, thereby improving reliability.
3Stability of the object's composition
If separate read port is added to implement reset before write, then stability of half-selected bit-cells is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the separate read port to serve multiple functions: it enables reading of data from bit-cells, provides feedback for the reset-before-write operation, and contributes to overall system stability. By making the read port multi-functional, the patent reduces the need for additional dedicated circuits, thereby mitigating the increase in device complexity while achieving improved stability for half-selected bit-cells.
Data Source
AI summary
An SRAM bit-cell with independent write and read ports and an architecture utilizing a feedback loop from the read port to the write port of half-selected bit-cells. This guarantees absolute data retention of all SRAM bit-cells not fully selected for write operation across a wide range of supply voltage spanning from the nominal voltage of a process to a sub-threshold range.