SRAM Handshake for Dual Interface Tag Data Integrity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing contactless tags and smart cards face challenges in efficiently managing data transfer between radio frequency (RF) and wired interfaces, leading to issues with data availability and integrity during communication.

Innovation Solution

An integrated circuit (IC) with a radio frequency (RF) interface, a wired interface, and volatile memory, along with a memory controller that detects when the last block of volatile memory is written or read, allowing for controlled data transfer and status indication between interfaces, enabling a dual interface tag for seamless data exchange.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data is transferred between RF and wired interfaces using shared volatile memory, then data exchange capability is improved, but data availability and integrity during communication deteriorate due to concurrent access conflicts

Engineering Contradiction:
Improvedata exchange capabilityVSAvoiddata availability and integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces an intermediary mechanism (memory controller with handshake signals) that mediates between the RF interface and wired interface when accessing shared volatile memory. This controller manages read/write operations, ensures data integrity, and coordinates access timing, preventing concurrent access conflicts while enabling data exchange between the two interfaces.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements feedback through handshake signals that provide status information about memory write completion and data readiness. The RF interface receives feedback when data is ready for reading, and the wired interface receives feedback when data transfer is complete, enabling synchronized and reliable data exchange without conflicts.

Inventive Principle:
Principle #23Feedback

2Speed

If volatile memory is used for fast data transfer between interfaces, then transfer speed is improved, but data loss risk increases when interface timing is mismatched

Engineering Contradiction:
Improvedata transfer speedVSAvoiddata loss prevention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by having the memory controller detect and signal when data is ready for transfer before the receiving interface actually reads it. The handshake mechanism prepares the system in advance, ensuring that data is available and synchronized before the next interface operation, preventing timing mismatches and data loss.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If the tag maintains idle state between communications, then power consumption is reduced, but response time increases when next communication occurs

Engineering Contradiction:
Improvepower consumptionVSAvoidresponse time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent uses preliminary action by preparing data in the volatile memory during the idle state before it is needed for transmission. The handshake mechanism pre-synchronizes data readiness, so when communication is initiated, the tag can quickly respond without processing delays, thus reducing response time while maintaining low power consumption during idle periods.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP2704021B1SRAM handshake
Publication Date: 2016.12.21 NXP BV
  • EP2704021B1 patent drawingFigure 1
  • EP2704021B1 patent drawingFigure 2
  • EP2704021B1 patent drawingFigure 3

AI summary

Various exemplary embodiments relate to an integrated circuit including: a RF interface; a wired interface connectable to a host; a volatile memory having a first block and a last block configured to store data transferred between the RF interface and the wired interface; and a memory controller configured to detect when the last block of the volatile memory has been written and to indicate that the volatile memory is ready to read. Various exemplary embodiments relate to a method performed by a tag including: determining that data is to be received on the first interface; blocking the second interface; writing data from the first interface to a volatile memory; detecting that the last block of the volatile memory has been written; unblocking the second interface; indicating that data is available for reading; blocking the first interface; and reading data from the volatile memory to the second interface.