SRAM Hybrid Write Assist for Low-Voltage Column Writeability
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Solution Overview
Problem
Existing SRAM technologies face challenges in maintaining optimal operating voltage during low and high voltage write operations due to process scaling, leading to issues such as high bitline resistance and strong pull-up transistors affecting writeability.
Innovation Solution
Implementing a hybrid write assist scheme combining bitcell supply self-discharge (BSSD) and negative bitline write assist (NBL) techniques to manage voltage levels during write operations, using NMOS and PMOS transistors to control voltage discharge and prevent floating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to improve density, then storage capacity increases, but writeability deteriorates due to high bitline resistance and strong pull-up transistors
Solution Approach 1:
The write assist function is segmented into two distinct circuits: BSSD circuit for voltage discharge and NBL circuit for voltage boosting. This segmentation allows each circuit to be optimized for its specific function, enabling successful writes in scaled memory cells where a single circuit would be insufficient
Solution Approach 2:
The patent combines BSSD and NBL circuits into a hybrid write assist scheme. The BSSD circuit discharges the bitcell supply voltage to weaken pull-up strength, while the NBL circuit simultaneously boosts the bitline voltage to overcome resistance, together resolving the writeability issue in scaled memory
2Reliability
If BSSD circuit discharges operating voltage to improve writeability, then write capability increases, but over-discharge may occur causing voltage to drop too low
Solution Approach 1:
The BSSD circuit incorporates feedback control where the discharge operation is monitored and automatically stopped when the operating voltage reaches a safe threshold level. This prevents over-discharge while maintaining sufficient voltage reduction to improve write capability
Solution Approach 2:
The circuit dynamically adjusts the discharge parameter (voltage level) during the write operation, reducing voltage from initial level to a controlled threshold, then stopping discharge to prevent further voltage drop below the safe operating level
3Stability of the object's composition
If PMOS transistor connects drain voltage to unselected column to prevent floating, then voltage stability improves, but excess voltage may cause over-discharge
Solution Approach 1:
The PMOS transistor circuit for unselected columns includes feedback control that monitors the operating voltage and adjusts the connection to the second drain voltage accordingly, maintaining voltage stability while preventing excess voltage that would cause over-discharge
Solution Approach 2:
The circuit applies different voltage control strategies to selected and unselected columns locally. Unselected columns receive controlled voltage through PMOS transistors to prevent floating, while selected columns undergo active discharge, with each column's voltage management tailored to its specific state
Data Source
AI summary
A method and circuit are provided for maintaining an operating voltage on a selected column with a plurality of bitcells in a memory when writing to the selected column. The method includes during an active write operation to the selected column, implementing an NMOS transistor NC to allow a bitcell-supply self-discharge (BSSD) to occur on the selected column, wherein the BSSD occurs by connecting a first drain voltage to an operating voltage connection of the selected column via the NMOS transistor NC to allow discharge of the operating voltage connection while limiting over-discharge of the selected column. The method further includes a PMOS select transistor PS to connect a second drain voltage to the operating voltage connection of the unselected column.