SRAM-Based Image Scaling Circuit for WiDi Signal Delay
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Solution Overview
Problem
Conventional image processing devices using Wireless Display (WiDi) technology face signal delays due to high memory bandwidth occupancy from frequent read and write operations on dynamic random access memory (DRAM), which can lead to undesirable user experiences in real-time image playback.
Innovation Solution
The use of static random access memory (SRAM) to store scaled image data, allowing the image scaling circuit to perform read and write operations independently of the video encoding circuit, reducing the need for external DRAM access and enhancing system response time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM is used to store and process image data, then the device can handle large video data amounts, but the frequent read and write operations occupy large memory bandwidth causing signal delays
Solution Approach 1:
The patent divides the memory system into two segments: DRAM for storing large video data amounts and SRAM for frequent read/write operations during image processing. This segmentation allows each memory type to operate independently, reducing bandwidth conflicts and signal delays while maintaining the ability to handle large video data amounts.
Solution Approach 2:
The patent introduces SRAM as an intermediary buffer between DRAM and the image processing circuits. The scaled image data is first stored in SRAM, which then provides data to the video encoding circuit. This intermediary approach reduces the frequency of DRAM access operations, thereby reducing signal delays while maintaining support for large video data amounts.
2Ease of manufacture
If the image scaling circuit performs read and write operations on DRAM, then the scaling process can be completed, but the memory bandwidth is heavily occupied reducing system response speed
Solution Approach 1:
The patent segments the memory hierarchy into DRAM for bulk data storage and SRAM for active processing. The image scaling circuit reads original image data from DRAM once, performs scaling operations, and stores the scaled image data in SRAM. This segmentation ensures the scaling process is completed while minimizing repeated DRAM access operations that would slow down system response.
Solution Approach 2:
The patent performs preliminary action by storing the scaled image data in SRAM immediately after the scaling process. This preliminary storage in the faster SRAM prepares the data for subsequent video encoding operations without requiring repeated DRAM access, thereby maintaining scaling process completion while improving overall system response speed.
3Productivity
If the MFE accesses image data from DRAM for encoding, then the video data can be processed, but the additional read operation further occupies memory bandwidth increasing delays
Solution Approach 1:
The patent segments the data storage and processing functions between DRAM and SRAM. The MFE accesses scaled image data from SRAM for video encoding rather than reading directly from DRAM. This segmentation enables continuous video data processing while reducing the frequency of DRAM read operations, thereby minimizing playback delays.
Solution Approach 2:
The patent uses SRAM as an intermediary buffer that holds the scaled image data between the image scaling circuit and the MFE. This intermediary approach allows the MFE to perform video encoding operations continuously without waiting for DRAM read operations, maintaining high productivity while reducing playback delays caused by frequent DRAM access.
Data Source
AI summary
An image processing device that converts original image data to target image data is provided. The image processing device includes: a static random access memory (SRAM); an image scaling circuit that generates scaled image data according to the original image data and stores the scaled image data to the SRAM; and a video encoding circuit that accesses the scaled image data from the SRAM and encodes the accessed scaled image data to generate the target image data. The target image data corresponds to an image frame. A part of the target image data is intra frame data encoded by an intra frame compression method, and the other part of the target image data is predicted frame data encoded by a predicted frame compression method.