SRAM In-Memory Computing Circuit for Low-Data-Movement AI Operations
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Solution Overview
Problem
In-memory computing systems face limitations in performance and power efficiency due to frequent data movement between processors and memory in Von Neumann architecture, particularly in performing matrix operations required for deep neural networks like CNNs, which leads to inefficiencies in operations like MAC and convolution operations.
Innovation Solution
The implementation of an in-memory computing (IMC) system that performs operations directly within the memory device, reducing data transmission by configuring the processor to input data to the memory device, where the memory device performs operations such as MAC, convolution, and logical operations like NOR, NAND, AND, OR, and XOR, using SRAM cells with inverters and transistors to minimize data movement and enhance power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data movement between processors and memory is frequent in Von Neumann architecture, then computational operations can be performed, but power efficiency deteriorates and performance is limited
Solution Approach 1:
The patent merges the memory storage function and computational processing function into a single integrated structure. SRAM cells are configured to perform logical operations (NOR, NAND, AND, OR, XOR) directly within the memory array, eliminating the need for separate processors. This integration allows data to be processed in-place without being transferred between memory and processing units, thereby improving power efficiency while maintaining computational performance.
2Device complexity
If data is stored and processed separately in Von Neumann architecture, then functional separation is achieved, but data transmission overhead increases
Solution Approach 1:
The patent combines storage and processing functions within the same SRAM cell structure. The memory cells are configured with additional transistors and inverters that enable logical operations to be performed directly on stored data. This eliminates the need for separate data transmission between memory and processing units, reducing time loss while maintaining functional separation through dedicated operation circuits.
3Loss of energy
If SRAM cells are configured to perform logical operations directly, then data movement is reduced, but circuit complexity increases
Solution Approach 1:
The patent implements a universal SRAM cell design that can perform multiple logical operations (NOR, NAND, AND, OR, XOR) using the same basic cell structure. The cell includes configurable transistor connections and inverter arrangements that can be switched between different operation modes. This multi-functionality reduces the need for separate dedicated circuits for each operation, thereby limiting the increase in overall circuit complexity while enabling data movement reduction.
4Loss of energy
If in-memory computing is implemented, then power efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the SRAM cell into distinct functional blocks: storage elements (cross-coupled inverters), operation control elements (transistors for selecting and configuring operations), and output elements. Each segment has a specific function that can be independently designed and manufactured. This segmentation allows for modular fabrication processes and simplifies quality control, thereby limiting the impact of increased manufacturing precision requirements while achieving power efficiency improvements through in-memory computing.
Data Source
AI summary
An apparatus includes a static random access memory (SRAM) cell including a first inverter and a second inverter, and a third inverter including a first inverter transistor and a second inverter transistor. An output terminal of the first inverter is connected to a source terminal of the second inverter transistor.