SRAM Initialization via Word Line Driver Reuse
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Solution Overview
Problem
Existing technologies for initializing data in SRAM memory cells are either slow due to large area requirements or result in area increases, making them inefficient for high-speed initialization while minimizing area usage.
Innovation Solution
A semiconductor device configuration that includes a plurality of word lines, pairs of bit lines, memory cells connected to these lines, a first transistor for power supply control, word line drivers, column switches, a precharge circuit, write circuits, and a control circuit that manages a reset signal to initialize memory cells quickly without increasing area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay circuit is added to shift word line rise timing for initialization, then memory cells can be initialized, but the area of the word line decoder unit increases
Solution Approach 1:
The word line drivers are designed to perform dual functions: normal word line activation during read/write operations and initialization of memory cells during reset operations. By controlling the activation state of the first transistors in memory cells through the same word line drivers, the patent eliminates the need for separate delay circuits or dedicated initialization circuits, thereby resolving the contradiction between initialization capability and decoder area.
2Reliability
If a dedicated bit line control circuit is added for initializing bit lines, then memory cell initialization is enabled, but the area of the SRAM macro increases
Solution Approach 1:
The existing bit line control circuits are designed to handle both normal read/write operations and initialization operations. During reset mode, these circuits control the column switches to drive bit lines to appropriate voltage levels for initialization, eliminating the need for dedicated initialization control circuits and preventing SRAM macro area increase.
Solution Approach 2:
Instead of adding specialized initialization circuits, the patent inverts the approach by using the normal operational circuits in reverse or alternative modes. The column switches and bit line control circuits that normally handle data operations are repurposed to perform initialization by driving bit lines to specific voltage states, thereby achieving initialization without area penalty.
3Reliability
If power supply to SRAM is blocked to erase data, then security is improved, but initialization at low temperature becomes difficult
Solution Approach 1:
The patent changes the approach from power supply blocking to active voltage control of bit lines for initialization. By controlling the voltage levels of bit lines through column switches during reset mode, the system can reliably initialize memory cells across a wide temperature range, including low temperatures where power blocking would fail to release trapped charges. This parameter change from passive power cutting to active voltage control resolves the contradiction between security and low-temperature operability.
Data Source
AI summary
Provided is a technology capable of initializing data in memory cells at a relatively high speed while suppressing an area increase. Based on a fact that the reset signal is turned to a high level, a control circuit of a semiconductor device turns a first transistor to an OFF state, a plurality of word lines to a selection state, a precharge circuit to the OFF state, column switches for writing to an ON state, and column switches for reading to the OFF state, causes write circuits to turn first bit lines and second bit lines to a low level and a high level, respectively, and initializes a plurality of memory cells.