Interchangeable SRAM Sub-layouts for Mask Reduction

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Solution Overview

Problem

Current SRAM cell layout designs require separate cell layouts and periphery circuits for different transistor structures, leading to increased research and development costs due to complex mask changes and varying cell sizes, which hinders efficient fabrication and sharing of structures.

Innovation Solution

A layout comprising interchangeable sub-layouts with variable covering patterns allows for the formation of different SRAM structures using the same first and second sub-layouts, enabling the same semiconductor substrate to be used for various SRAM configurations by adjusting the third sub-layout, thereby reducing the need for multiple masks and simplifying the fabrication process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate cell layouts are designed for different transistor structures, then the drive current requirements for different transistors can be met, but the device complexity and development cost increase

Engineering Contradiction:
Improvedrive current matchingVSAvoidcell layout complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a standardized cell layout that can accommodate different transistor structures (single-fin, multi-fin, different gate lengths) through parameter adjustment rather than requiring separate layout designs. The common layout framework allows the same basic structure to serve multiple functions by varying fin count, gate dimensions, and transistor arrangement while maintaining compatibility with standard fabrication processes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If different fin frames are used for different SRAM cells, then the performance requirements can be satisfied, but the manufacturing process complexity increases

Engineering Contradiction:
ImproveSRAM performanceVSAvoidfabrication process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent employs parameter changes by maintaining a consistent cell layout framework while allowing adjustment of specific parameters such as fin count, gate length, gate width, and transistor dimensions to meet different performance requirements. This approach enables customization of SRAM cell characteristics without changing the fundamental layout structure, thereby simplifying the fabrication process and mask design.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If multiple masks with different cell layouts are used, then different SRAM structures can be fabricated, but the mask area and development cost increase

Engineering Contradiction:
ImproveSRAM structure varietyVSAvoidmask area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent applies universality by creating a standardized cell layout that can be used across different SRAM designs, eliminating the need for multiple specialized masks. The same basic layout framework can generate various SRAM structures by modifying transistor parameters (fin count, gate dimensions) within the standardized design, thereby reducing mask area requirements and development costs while maintaining structure variety.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9679902B2Layouts and fabrication methods for static random access memory
Publication Date: 2017.06.13 SEMICON MFG INT (SHANGHAI) CORP
  • US9679902B2 patent drawing
  • US9679902B2 patent drawing
  • US9679902B2 patent drawing

AI summary

A layout of a random access memory is provided. The layer comprises a first sub-layout having a first pattern including a first number (N1) of first patterns and an adjacent second pattern having a second number (N2) of second patterns; a second sub-layout having a first gate pattern and a second gate pattern; and an interchangeable third sub-layout having covering patterns variable for forming different static random access memory when used with the first sub-layout and the second sub-layout.