SRAM Bit Cell Interconnect Layout for Backside Power Routing
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Solution Overview
Problem
Existing semiconductor devices and fabrication methods face challenges in efficiently scaling down while maintaining complexity and functionality, particularly in the formation of semiconductor integrated circuits (ICs) due to the increased complexity of processing and manufacturing.
Innovation Solution
The implementation of a SRAM bit cell design with a back side power rail and specific interconnect layouts, including front and back side interconnect structures, which allows for efficient routing of conductors and power rails, enhancing the integration of GAA transistors in SRAM bit cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing and manufacturing complexity increases
Solution Approach 1:
The patent introduces a back-side interconnect structure that routes power rails and ground lines through the substrate back surface, adding a third dimension to the interconnect architecture. This separates front-side signal routing from back-side power distribution, reducing congestion and simplifying manufacturing processes while enabling continued scaling of device geometry
2Quantity of substance
If functional density is increased by scaling down, then more devices fit per chip area, but the complexity of fabrication processes increases
Solution Approach 1:
The interconnect structure is segmented into front-side components (word lines, bit lines, select lines) and back-side components (power rails, ground lines). This segmentation allows independent optimization and fabrication of each interconnect layer, simplifying the overall manufacturing process while supporting high device density through efficient space utilization
3Productivity
If interconnect routing is optimized for high density, then more transistors can be integrated, but manufacturing complexity increases
Solution Approach 1:
By utilizing the substrate back surface for power and ground routing, the patent adds a dimensional layer to the interconnect architecture. This separates power distribution from signal routing, reducing interconnect complexity on the front side while maintaining high transistor integration density through efficient three-dimensional space utilization
Data Source
AI summary
Embodiments of the present disclosure relate to a memory bit cell including two doped regions and four gate structures. Bit line, bit line bar, and word line of the bit cell are formed on a front side of the bit cell and power rails are formed on a back side of the bit cell. In some embodiments, each bit cell includes two word lines.