SRAM Interconnect Capacitor Layout for Higher Capacitance
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Solution Overview
Problem
Current static random-access memory (SRAM) devices face challenges in increasing capacitor capacitance without additional photomasks and manufacturing processes, which limits their electrical performance.
Innovation Solution
A manufacturing method for SRAM devices that forms a capacitor within a metal interconnect structure, using a lower metal layer as part of the capacitor, with electrode layers deposited via MOCVD and SFD, and dielectric layers to increase capacitance while integrating with existing 2-transistor-SRAM processes, allowing for relaxed process conditions and reduced impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is formed using traditional methods on the substrate, then the manufacturing process is simple, but the capacitance is limited and electrical performance is insufficient
Solution Approach 1:
The invention merges the capacitor formation process with the existing metal interconnect structure fabrication. The lower electrode of the capacitor is formed using the same metal layer deposition process as the interconnect layers, and the upper electrode is formed using the same process as subsequent metal layers. This integration allows the capacitor to be manufactured within the existing process flow without adding separate capacitor fabrication steps, thereby improving electrical performance while avoiding increased manufacturing complexity
Solution Approach 2:
The invention transitions from forming capacitors in the planar substrate dimension to forming capacitors within the vertical metal interconnect structure. By utilizing the height dimension of the metal interconnect layers, the capacitor achieves increased capacitance through the vertical stacking of electrodes and dielectric layers, effectively adding a dimensional aspect to capacitor formation that was not available in traditional substrate-based approaches
2Reliability
If additional photomasks and manufacturing processes are used to increase capacitance, then the capacitance improves, but the manufacturing complexity and cost increase
Solution Approach 1:
The metal layers in the interconnect structure serve dual functions: as interconnect conductors and as capacitor electrodes. The same metal deposition processes that create the interconnect layers also create the capacitor electrodes, making the manufacturing process universal and eliminating the need for additional photomasks or specialized capacitor fabrication steps. This multi-functionality approach increases capacitance while maintaining ease of manufacture
Solution Approach 2:
The existing metal interconnect structure provides the framework and materials needed for capacitor formation. The metal layers that would otherwise only serve as interconnects automatically become the capacitor electrodes when properly patterned and stacked with dielectric layers. This self-service approach allows the structure to serve both purposes without requiring external additional processes or materials
3Reliability
If the capacitor is formed with greater height using metal interconnect structure, then the capacitance increases significantly, but the process integration complexity increases
Solution Approach 1:
The formation of the capacitor's lower electrode is merged with the metal interconnect layer deposition process. By using the same sputtering or CVD processes to deposit both the interconnect metal layers and the capacitor electrode layers, the invention achieves vertical stacking for increased capacitance while maintaining process integration simplicity. The same equipment and process parameters are used throughout
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly increases capacitance by leveraging the height of the metal interconnect structure, reduces impedance, and integrates seamlessly with existing processes, enhancing the electrical performance of SRAM devices.
Implementation Method 1
a method of forming the first electrode layer includes metal-organic chemical vapor deposition (MOCVD)
Implementation Method 2
a method of forming the second electrode layer includes supercritical fluid deposition (SFD), physical vapor deposition (PVD), or a combination thereof
Implementation Method 3
a method of forming the second electrode layer includes supercritical fluid deposition (SFD), physical vapor deposition (PVD), or a combination thereof
Data Source
AI summary
A manufacturing method of a SRAM memory device includes forming two transistors on a substrate, forming an inner dielectric layer covering the two transistors, forming contacts in the inner dielectric layer for coupling to source nodes of the two transistors, forming a metal interconnect structure on the inner dielectric layer, wherein a portion of an n-th metal layer of the metal interconnect structure is utilized as a lower metal layer, wherein n≥1. An opening is formed in the metal interconnect structure to expose the lower metal layer, and then a capacitor is formed in the opening. The capacitor includes the lower metal layer, a first electrode layer, a dielectric layer, a second electrode layer, and an upper metal layer from bottom to top. The upper metal layer is a portion of an m-th metal layer of the metal interconnect structure, wherein m≥n+1.