SRAM Interconnect Layout With Double Word Lines and Wide M1 Bit Lines
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Solution Overview
Problem
The increased resistance and capacitance of interconnects in advanced IC technology nodes lead to signal delays, affecting the performance of memory devices like SRAM, which are required to operate at ever-faster speeds.
Innovation Solution
Configuring bit lines as the widest metal lines in the metal one layer to minimize capacitance and resistance, using a double word line structure with word line straps, and implementing a double voltage line structure to reduce resistance, along with optimizing via shapes and dimensions to enhance interconnect structures for improved electrical characteristics and SRAM density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interconnect dimensions are scaled down to increase functional density, then production efficiency and cost are improved, but resistance and capacitance of interconnects increase causing signal delays
Solution Approach 1:
The patent applies different metal materials to different interconnect layers based on their specific electrical performance requirements. Copper is used in lower layers where lower resistance is critical for signal integrity, while cobalt is used in upper layers where lower capacitance is more important. This local differentiation of material properties resolves the contradiction by optimizing each layer's electrical characteristics for its specific function while maintaining overall scaling benefits.
Solution Approach 2:
The patent employs a composite interconnect structure using multiple metal materials (copper and cobalt) with complementary properties. By combining copper's low resistance characteristic with cobalt's low capacitance characteristic in a multilayer architecture, the system achieves both reduced signal delay and maintained scaling efficiency, resolving the technical contradiction between productivity and signal delay.
2Area of stationary object
If interconnect dimensions are scaled down to increase functional density, then chip area utilization is improved, but resistance and capacitance increase affecting memory performance
Solution Approach 1:
The patent differentiates material selection by interconnect layer location and function. Copper is deployed in layers where resistance dominates performance (lower layers), while cobalt is used where capacitance is the limiting factor (upper layers). This local quality differentiation maintains memory performance reliability despite reduced interconnect dimensions and increased chip area utilization.
Solution Approach 2:
By implementing a composite material system with copper and cobalt in a multilayer interconnect structure, the patent achieves both high chip area utilization and maintained memory performance. The complementary electrical properties of the two materials compensate for the effects of scaling, ensuring reliability is preserved while maximizing area efficiency.
3Reliability
If bit line width is increased to minimize resistance, then electrical conductivity is improved, but capacitance increases
Solution Approach 1:
The patent resolves the resistance-capacitance tradeoff by transitioning from a single-dimensional width optimization to a multidimensional approach across multiple metal layers. Instead of simply increasing bit line width in one layer, the system distributes interconnect functions across multiple layers with different materials, optimizing both resistance and capacitance through vertical dimensionality rather than horizontal scaling.
Solution Approach 2:
The patent uses composite materials (copper and cobalt) with different electrical characteristics to resolve the resistance-capacitance contradiction. Copper provides low resistance in layers where current density is high, while cobalt provides low capacitance in layers where signal coupling is critical, achieving both improved conductivity and reduced capacitance through material composition rather than geometric scaling.
4Ease of manufacture
If word line structure is simplified to reduce manufacturing complexity, then ease of manufacture is improved, but resistance increases affecting signal routing
Solution Approach 1:
The patent segments the word line function across multiple metal layers rather than attempting to implement it in a single simplified structure. By dividing the word line routing into multiple layers (with copper in lower layers and cobalt in upper layers), the system maintains signal routing reliability through distributed low-resistance paths while keeping each individual layer's manufacturing complexity manageable.
Solution Approach 2:
The patent uses composite materials to maintain signal routing reliability without increasing manufacturing complexity. The multilayer copper-cobalt structure provides low resistance paths for word lines through the combination of materials' complementary properties, achieving reliable signal routing while using standard multilayer fabrication processes that don't significantly increase manufacturing complexity.
Data Source
AI summary
Configurations of metal layers of interconnect structures, and methods of fabrication thereof, are disclosed for memories, such as a static random-access memory (SRAM). For example, bit lines are placed in a metal one (M1) layer, which is a lowest metallization level of an interconnect structure of a memory cell, to minimize bit line capacitance, and configure bit lines as the widest metal lines of the metal one layer to minimize bit line resistance. In some embodiments, the interconnect structure has a double word line structure to reduce word line resistance. In some embodiments, the interconnect structure has a double voltage line structure to reduce voltage line resistance. In some embodiments, jogs are added to a word line and/or a voltage line to reduce its respective resistance. In some embodiments, via shapes of the interconnect structure are configured to reduce resistance of the interconnect structure.