SRAM Inversion Writing Circuit for NBTI Mitigation
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Solution Overview
Problem
P-channel field effect transistors in SRAMs suffer from negative bias temperature instability (NBTI), leading to threshold voltage shifts and reduced current driving ability, which can break the latch balance and result in data loss, especially when mixed with inverted data in memory cells.
Innovation Solution
A semiconductor memory device with a memory cell array, inversion writing circuit, address counter, decoder, and data latch/writing control circuit that inverts data during standby cycles to maintain latch balance by alternating data states in memory cells, ensuring accurate data reading and writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is stored in memory cells with mixed inverted and non-inverted states, then the memory can store diverse data patterns, but the latch balance is broken and data accuracy deteriorates
Solution Approach 1:
The patent applies periodic action by systematically inverting data in memory cells at regular intervals defined by a counter. The counter increments with each access and triggers inversion when reaching a predetermined value, creating a periodic pattern that alternates between inverting and non-inverting operations. This periodic inversion maintains latch balance while preserving data storage versatility.
Solution Approach 2:
The patent employs preliminary action by proactively inverting data in memory cells before the NBTI effect can cause significant threshold voltage shifts. The systematic inversion occurs during normal operation based on counter values, preventing the accumulation of degradation effects that would otherwise break latch balance and corrupt data.
2Power
If P-channel field effect transistors operate in ON state for long periods under high temperature, then current driving ability is maintained initially, but threshold voltage rises and current driving ability falls due to NBTI
Solution Approach 1:
The patent applies periodic action by systematically inverting data in memory cells at regular intervals defined by a counter. The counter increments with each access and triggers inversion when reaching a predetermined value, creating a periodic pattern that alternates between inverting and non-inverting operations. This periodic inversion maintains latch balance while preserving data storage versatility.
Solution Approach 2:
The patent employs preliminary action by proactively inverting data in memory cells before the NBTI effect can cause significant threshold voltage shifts. The systematic inversion occurs during normal operation based on counter values, preventing the accumulation of degradation effects that would otherwise break latch balance and corrupt data.
3Reliability
If inversion writing is performed continuously in all memory cells, then latch balance is maintained, but device complexity and operation complexity increase
Solution Approach 1:
The patent applies segmentation by dividing the memory cell array into different groups based on the counter value. Instead of uniformly inverting all memory cells, the inversion operation is selectively applied to specific segments or groups of cells. This segmented approach reduces the overall inversion frequency and simplifies control circuit requirements while still maintaining latch balance across the entire array.
Solution Approach 2:
The patent employs local quality by applying inversion operations selectively to specific memory cells or regions rather than uniformly across the entire array. The counter-based control mechanism determines which local regions undergo inversion, allowing different parts of the memory array to have different inversion states. This localized approach reduces control complexity while maintaining overall latch balance.
Data Source
AI summary
The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the memory cell is executed.