SRAM Readout Using Keeper Circuits to Reduce Footprint
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Solution Overview
Problem
Next-generation pixel-array densities and increased process/voltage/temperature sensitivity challenge the reliability and speed of data readout in imaging integrated circuits, leading to complex and area-consuming timing generators that compromise between readout and bit-error rates.
Innovation Solution
The implementation of small-footprint keeper-based readout circuitry replaces conventional SRAM sense-amplifiers, simplifying SRAM cell access and bitline sampling operations, and using a PVT-impervious keeper-clock design to omit the complex timing generator, enabling faster readout and lower bit error rates while reducing the readout circuitry footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional sense-amplifier-based SRAM readout is used, then data readout function is achieved, but timing-generator complexity and footprint increase
Solution Approach 1:
The patent extracts and removes the complex timing generator from the SRAM readout circuitry. By using keeper circuits that inherently provide timing-insensitive operation, the patent eliminates the need for precise timing control circuits, thereby reducing device complexity while maintaining readout reliability through the keeper-based latch mechanism
Solution Approach 2:
The patent replaces the complex, PVT-sensitive timing generator with simple keeper circuits that are area-efficient and robust. The keeper circuits act as disposable, simple structures that provide reliable data retention without requiring complex timing control, effectively trading complexity for simplicity and robustness
2Device complexity
If conventional sense-amplifier-based SRAM readout is used, then data readout function is achieved, but circuit footprint increases
Solution Approach 1:
The patent removes the large sense amplifier circuits and replaces them with compact keeper circuits. This extraction of bulky timing-sensitive components significantly reduces the readout circuitry footprint while the keeper-based architecture maintains data integrity and lowers bit-error rates through its inherent latch mechanism
Solution Approach 2:
The patent uses keeper circuits that replicate the essential data-retention function of sense amplifiers but in a much more compact form. The keeper circuits copy the data-holding capability without the associated complexity and area requirements of traditional sense amplifiers, achieving area efficiency while maintaining reliability
3Reliability
If timing margins are increased to improve reliability, then bit-error rate decreases, but readout speed decreases
Solution Approach 1:
The patent creates a dynamic readout system where keeper circuits continuously maintain data validity without requiring fixed timing margins. The keeper-based architecture dynamically adapts to PVT variations, allowing faster readout speeds while maintaining reliability by eliminating the need for conservative timing setup and hold requirements
4Quantity of substance
If pixel-array density is increased, then imaging resolution is improved, but readout circuitry area consumption increases
Solution Approach 1:
The patent extracts and eliminates the bulky sense amplifier and timing generator circuits that consume significant die area. By replacing these with compact keeper circuits, the patent reduces the readout circuitry footprint, thereby preserving precious die area that can be allocated to expanding the pixel array and improving imaging resolution
Data Source
AI summary
Conventional SRAM sense-amplifiers are replaced by small-footprint keeper circuits that enable single-ended SRAM readout without bitline precharge, simplifying and relaxing the timing of SRAM cell access and bitline sampling operations and thus enabling potentially faster readout operation and/or lower bit error rate.