SRAM Layout Pattern with L-Shaped Gate Structure
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Solution Overview
Problem
Current SRAM architectures face challenges in producing desirable patterns as the gap of the exposure process decreases, making it difficult to enhance exposure quality and improve the performance of pull-down transistors.
Innovation Solution
The proposed SRAM layout pattern includes L-shaped or step-shaped gate structures for pull-down transistors, which cross multiple diffusion regions, increasing the read current and allowing for a simpler and more stable connection with a single contact plug, thereby enhancing the performance of pull-down transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SRAM layout is used, then manufacturing process is simpler, but exposure quality deteriorates as gap decreases
Solution Approach 1:
The gate structure is segmented into multiple portions (first portion, second portion, third portion) that cross different diffusion regions separately. This segmentation allows each portion to be optimized independently for exposure quality while maintaining overall functional integrity, directly addressing the exposure quality deterioration issue.
Solution Approach 2:
The gate structure transitions from a conventional linear arrangement to a multi-dimensional L-shaped or stepped configuration. This dimensional change allows the gate to cross multiple diffusion regions in different directions, improving exposure quality by creating larger effective gaps that are less susceptible to exposure process limitations.
2Reliability
If conventional gate structure is used, then device area is smaller, but read current of pull-down transistor is insufficient
Solution Approach 1:
The gate structure merges multiple gate portions (first, second, and third portions) into a single integrated L-shaped or stepped structure that simultaneously controls multiple diffusion regions. This merging increases the effective gate width and thus the read current of the pull-down transistor without requiring separate structures, achieving current enhancement while controlling area growth.
Solution Approach 2:
The multi-port gate structure serves multiple functions: it acts as the gate for the pull-down transistor, provides interconnection between different diffusion regions, and enhances the read current through increased effective width. This multi-functionality allows the structure to improve reliability while minimizing additional area consumption.
3Device complexity
If multiple contact plugs are used for connection, then connection stability is higher, but device complexity increases
Solution Approach 1:
Multiple contact functions are merged into a single contact plug that connects to the multi-port gate structure. This consolidation reduces the number of contact plugs required while maintaining connection stability, as the multi-port gate structure provides multiple connection points within a single unified element, thereby reducing device complexity.
Data Source
AI summary
The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least two inverters coupled to each other for storing data, each inverter comprising an L-shaped gate structure on a substrate, the L-shaped gate structure includes a first portion arranged along a first direction and a second portion aligned along a second direction, wherein the first portion crosses a first diffusion region to form a pull-up device, and the first portion crosses a second diffusion region and a third diffusion region to form a pull-down device, and each of the inverters includes a local interconnection layer, crossing the second diffusion region and the third diffusion region.