SRAM Latch Circuit Clockless Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SRAM memory devices require synchronization between external clock signals and data signals for latch circuits, which can lead to inefficiencies and increased complexity in memory access operations.
Innovation Solution
A latch circuit configuration that latches global bit line signals in response to data signals from the memory array, eliminating the need for an external clock signal and simplifying the synchronization process by using signals from the sense amplifier to enable and disable the latch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external clock signals are used to synchronize latch circuits, then reliable timing control is achieved, but device complexity and access time are increased
Solution Approach 1:
The patent removes the external clock signal from the latch circuit synchronization process. Instead of using a separate clock signal, the latch is directly controlled by the data signal from the sense amplifier, eliminating the need for clock distribution networks and reducing device complexity while maintaining reliable timing control through the inherent signal timing.
Solution Approach 2:
The latch circuit uses the data signal itself to trigger the latching action. The sense amplifier output directly enables the latch without requiring an external clock, allowing the circuit to self-synchronize using its own operational signals. This eliminates the need for separate clock generation and distribution infrastructure.
2Reliability
If external clock signals are used for latch synchronization, then timing control is achieved, but memory access time is increased
Solution Approach 1:
By removing the external clock signal requirement, the patent eliminates the additional timing overhead associated with clock distribution and synchronization. The latch is triggered directly by the sense amplifier output, reducing memory access time while maintaining reliable timing control through the direct signal path.
3Reliability
If clock synchronization is implemented, then latch control is achieved, but the number of circuit components increases
Solution Approach 1:
The patent extracts and removes the clock signal generation and distribution components from the memory circuit. The latch control is achieved using only the sense amplifier output signal, eliminating counters, clock generators, and distribution networks, thereby reducing the total number of circuit components while maintaining reliable latch control.
Data Source
AI summary
A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.