SRAM Latch-Up Prevention via NWELL Power Sequencing
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Solution Overview
Problem
Gate enhanced drain leakage (GEDL) in static random access memory (SRAM) arrays contributes significantly to system on a chip (SOC) leakage, leading to potential latch-up issues during power-up, which can cause malfunction or destruction of the SRAM die.
Innovation Solution
A system on a chip (SOC) design that includes a memory system with a SRAM bank and a memory controller, utilizing two switches to control the power supply to SRAM storage cells, where the NWELL power signal is routed to the bulk of the transistor before the SRAM array power signal, preventing latch-up by ensuring controlled power-up sequencing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the SRAM array power signal is applied before the NWELL power signal, then the SRAM array can be powered up quickly, but latch-up occurs causing malfunction or destruction of the SRAM die
Solution Approach 1:
The patent applies preliminary action by enabling the NWELL power signal before the SRAM array power signal. Specifically, the memory controller is configured to apply the second power signal (NWELL) to the NWELL region prior to applying the first power signal (SRAM array power) to the SRAM array. This preliminary establishment of proper potential in the NWELL region prevents latch-up from occurring when the SRAM array is subsequently powered up, thus resolving the contradiction between fast power-up and reliability.
2Loss of time
If the SRAM array power signal is applied before the NWELL power signal, then power-up is faster, but GEDL increases leading to latch-up issues
Solution Approach 1:
The patent uses preliminary action by pre-establishing the NWELL power signal before applying the SRAM array power signal. The memory controller enables the second power signal (NWELL) prior to enabling the first power signal (SRAM array power), ensuring that the NWELL region is already at the correct potential when the SRAM array is powered up. This prevents gate-enhanced drain leakage (GEDL) from causing latch-up, thus reducing harmful leakage effects while maintaining acceptable power-up timing.
3Reliability
If proper power sequencing is implemented to prevent latch-up, then reliability improves, but power-up control complexity increases
Solution Approach 1:
The patent introduces an intermediary element - the memory controller - that manages the power sequencing between the NWELL power signal and the SRAM array power signal. The memory controller is configured to generate and apply the second power signal (NWELL) before applying the first power signal (SRAM array power). This intermediary control mechanism ensures proper sequencing and prevents latch-up while keeping the complexity localized to the memory controller rather than distributed throughout the SRAM array.
Data Source
AI summary
A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.