SRAM Layout Pattern With Additional Fin Structures
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Solution Overview
Problem
Current SRAM layouts face issues with current inconsistency due to uneven stress caused by large insulating layers around transistors, leading to asymmetry and reduced device quality.
Innovation Solution
The introduction of additional fin structures or extended fin structures to reduce the stress on transistors by adjusting the surrounding insulating layer area, thereby improving symmetry and current consistency between transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SRAM layout is used with standard fin structures, then manufacturing process is simple, but current inconsistency occurs due to uneven stress from large insulating layers around transistors
Solution Approach 1:
The patent applies local quality by introducing additional fin structures specifically between certain transistor pairs (e.g., between PG1 and RPG, between PD1 and RPD) to create localized stress compensation zones. This targeted approach adjusts the insulating layer area only where needed, rather than uniformly across all transistors, thereby improving current consistency in specific critical paths while maintaining manufacturing simplicity.
2Reliability
If additional fin structures are added to reduce insulating layer area and stress, then current difference between transistors is reduced, but layout complexity increases
Solution Approach 1:
The patent deliberately introduces asymmetry in the fin structure arrangement by adding fins only in specific locations between certain transistor pairs. This asymmetric layout creates balanced stress distribution across different transistor types (nMOS and pMOS) by compensating for the inherently different insulating layer areas around each transistor type, thereby improving overall transistor symmetry and current matching.
Data Source
AI summary
A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first pass gate transistor PG1, a second pass gate transistor PG2, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PG1 and the fin structure of the second read transistor RPG.