SRAM Cell Layout With Asymmetric Active Area for Low Leakage
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Solution Overview
Problem
SRAM cells face challenges in minimizing standby leakage current (Isb) due to process variations and shrinking device sizes, particularly in 6T storage cells, which affects power consumption and access speed, especially during read operations.
Innovation Solution
The design incorporates an irregular active area configuration with a stem and wing portions and tooth portions, optimizing the overlap between the gate electrode and active area to reduce junction and gate leakage, and a butted contact structure that minimizes overlap with the isolation feature, allowing for a reduced standby current while maintaining compatibility with existing semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional 6T storage cell design is used, then device size can be maintained, but standby leakage current increases due to contact leakage to shallow trench isolation and gate overlap leakage
Solution Approach 1:
The patent applies asymmetry by modifying the symmetric conventional 6T SRAM cell layout into an asymmetric configuration where the active area has an irregular shape with a stem portion and wing portions. The gate electrode is positioned to overlap only with the stem portion, creating asymmetric overlap regions that reduce gate leakage current while maintaining proper transistor functionality. This asymmetric design breaks the symmetry of conventional layouts to minimize leakage paths.
Solution Approach 2:
The patent implements local quality by creating different geometric configurations in different regions of the active area. The stem portion has a specific width and position optimized for gate overlap control, while the wing portions extend laterally to maintain transistor performance. The isolation feature is positioned to be spaced from the gate electrode, creating localized regions with different electrical characteristics to minimize leakage at critical interfaces.
2Area of moving object
If device size is reduced, then integration density improves, but standby leakage current increases due to increased process variations and contact leakage
Solution Approach 1:
In scaled-down devices, the patent uses asymmetry to optimize the limited space by having the gate electrode overlap only with the narrow stem portion rather than the full width active area. This asymmetric arrangement reduces gate leakage in miniaturized devices where leakage paths become more significant relative to device dimensions, enabling continued scaling while controlling standby current.
Solution Approach 2:
The patent applies local quality optimization for small devices by carefully controlling the local geometry at the gate-isolation interface. The isolation feature is positioned at a specific distance from the gate electrode, and the active area width under the gate is locally reduced at the stem portion. These localized geometric controls are particularly effective in small devices where absolute dimensions are reduced but leakage mechanisms remain significant.
3Speed
If gate and active area overlap is increased, then transistor performance improves, but gate leakage current increases
Solution Approach 1:
The patent implements local quality by creating a differentiated active area geometry where the width under the gate electrode (stem portion) is narrower than the full active area width. This local reduction in overlap area at the gate interface reduces gate leakage current, while the overall active area (including wing portions) maintains sufficient dimensions for proper transistor performance and access speed.
Solution Approach 2:
The patent segments the active area into functionally distinct regions: the stem portion that overlaps with the gate electrode for controlled gate leakage, and the wing portions that extend laterally to maintain transistor performance. This segmentation allows independent optimization of gate leakage control and transistor speed characteristics.
Data Source
AI summary
An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.