SRAM Layout Pattern Using Non-Rectangular Regions
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Solution Overview
Problem
Conventional SRAM cells face challenges in achieving increased stability and writing speed while optimizing space usage, as they often require a larger area due to the arrangement of transistors and sharing of diffusion regions.
Innovation Solution
The proposed layout pattern for a 6T-SRAM cell includes six transistors arranged in a non-rectangular region, with some transistors sharing a diffusion region, allowing for efficient use of space and reducing the overall area, and features an access transistor and a switching transistor connected to independent word and mode lines to control the latching state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are arranged in a conventional rectangular layout, then the device area is larger, but the stability and writing speed are reduced
Solution Approach 1:
The patent applies asymmetry by arranging six transistors in a non-rectangular layout pattern where the transistors are positioned with different spacing relationships. Specifically, the first through fourth transistors form a asymmetric configuration with shared diffusion regions, while the fifth and sixth transistors are positioned to optimize access paths. This asymmetric arrangement improves stability and writing speed by optimizing the electrical characteristics and signal paths without requiring a larger rectangular area.
2Area of stationary object
If transistors are closely arranged to reduce device area, then the space usage is optimized, but the writing speed may be affected
Solution Approach 1:
The patent applies segmentation by dividing the SRAM cell into distinct functional regions with specific transistor groupings. The first four transistors form a latch circuit with shared diffusion regions, while the fifth and sixth transistors serve as access transistors with separate diffusion regions. This segmentation allows closely arranged transistors to maintain optimized writing speed by preserving distinct signal paths and reducing interference, even though the overall device area is reduced.
3Device complexity
If a conventional 6T-SRAM layout is used, then the transistor arrangement is simple, but the device area is larger and stability is reduced
Solution Approach 1:
The patent applies merging by combining the diffusion regions of the first and second transistors, as well as the third and fourth transistors, to form shared diffusion regions. This merging reduces the number of separate diffusion regions from eight to four, thereby reducing device area and improving stability through better electrical characteristics. The layout remains relatively simple as it maintains the basic 6T-SRAM structure while optimizing the diffusion region configuration.
Data Source
AI summary
The present invention provides a layout pattern of a memory device composed of static random access memory (SRAM), comprising four memory units located on a substrate, each memory unit being located in a non-rectangular region, the four non-rectangular regions combine a rectangular region, wherein each memory unit comprises a first inverter comprising a first pull-up transistor (PL1) and a first pull-down transistor (PD1), a second inverter comprises a second pull-up transistor (PL2) and a second pull-down transistor (PD2), an access transistor (PG) and a switching transistor (SW), wherein the source of the PG is coupled to an input terminal of the first inverter and a drain of the SW, a source of the SW is coupled to an output of the second inverter, wherein the PD1, the PD2, the SW, and the PG comprise a first diffusion region, the PL1 and the PL2 comprise a second diffusion region.