SRAM Leakage Reduction via Balanced Voltage Biasing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Static random-access memory (SRAM) devices face challenges in reducing power leakage during sleep retention mode due to sensitivity of source voltage biasing across process corners, which limits the effectiveness of conventional current leakage reduction methods.
Innovation Solution
A method and apparatus for process-tolerant current leakage reduction in SRAM using a balanced voltage biasing circuit with a pair of semiconductor devices (N-type and P-type) that adjust the operational parameter of the semiconductor devices to optimize the voltage level for data retention mode, ensuring robustness across different process corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If source voltage is raised to reduce power leakage in sleep retention mode, then power consumption is reduced, but the voltage becomes highly sensitive across process corners and may fail to meet rail-to-rail voltage requirements for data retention
Solution Approach 1:
The patent changes the voltage parameter dynamically by introducing an adjustable bias voltage to the source of the memory array. This bias voltage is tuned to compensate for process corner variations, allowing the system to maintain optimal voltage levels for both leakage reduction and data retention across different manufacturing processes. The bias voltage acts as a compensating parameter that shifts the operating point of the memory cells.
Solution Approach 2:
The patent implements a feedback mechanism where the bias voltage is adjusted based on process corner detection or characterization. The system measures or predicts the process corner conditions and applies appropriate bias adjustments to maintain reliable operation. This closed-loop approach ensures that the voltage levels adapt to actual process variations, preventing data retention failures while maximizing leakage reduction.
2Loss of energy
If conventional source voltage biasing is used to reduce leakage, then power consumption decreases, but the solution lacks robustness across different process corners
Solution Approach 1:
The patent introduces an adjustable bias voltage parameter that can be tuned for different process corners. Instead of using a fixed source voltage raise, the system dynamically adjusts the bias voltage level based on the specific process corner conditions. This parameter adaptation allows the same circuit architecture to achieve optimal leakage reduction across fast, slow, and typical process corners without sacrificing reliability.
Solution Approach 2:
The patent transforms the static source voltage biasing into a dynamic system where the bias voltage can be adjusted in response to process variations. The bias voltage is not fixed but can be programmed or tuned based on manufacturing data or operational conditions. This dynamic adjustment capability provides adaptability across process corners while maintaining continuous leakage reduction benefits.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory device biasing circuit is disclosed, the circuit having a pair of semiconductor devices coupled to receive a supply voltage having a supply voltage level suitable for operating a memory device in an active mode and operable for providing an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the memory device in a data retention mode. The pair of semiconductor devices includes a first semiconductor device; and, a second semiconductor device that includes an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices includes each of an N-type semiconductor device and a P-type semiconductor device. The memory device biasing circuit further includes a bias adjustment circuit coupled to the second semiconductor device and configured to adjust the operation of the second semiconductor device based on the supply voltage.