SRAM Leakage Control via Distributed Clamping Transistors
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Solution Overview
Problem
The increasing leakage current in SRAMs due to microfabrication advancements is not effectively addressed by existing technologies, leading to increased chip size and area requirements, particularly due to the need for shielding bias potential lines and separate N- and P-type wells, which complicates the arrangement of clamping PMOS transistors and power-supply interruption switches.
Innovation Solution
A semiconductor memory device with a memory cell array using metal insulator semiconductor (MIS) transistors, featuring a switching element group that disconnects the source potential line from the ground in sleep mode, and a bias generation circuit in the peripheral area to control the bias potential of MIS transistors, reducing leakage current without the need for extensive shielding and separate wells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clamping PMOS transistors are arranged along the ends of the cell array, then the bias potential can be applied to control leakage current, but the bias potential line becomes long and requires shielding, increasing the device area
Solution Approach 1:
The patent moves the clamping PMOS transistors from the traditional arrangement along the ends of the cell array (one-dimensional arrangement) to a distributed arrangement within the cell array area (two-dimensional arrangement). This dimensional change allows the bias potential line to be shorter and eliminates the need for shielding, thereby reducing the device area while still effectively controlling leakage current.
Solution Approach 2:
The patent applies different functions to different parts of the cell array by distributing clamping PMOS transistors throughout the cell array area rather than concentrating them at the ends. Each local region has its own clamping transistor, providing localized leakage current control and eliminating the need for long bias potential lines that would require shielding.
2Reliability
If both N- and P-type wells are provided for NMOS and PMOS transistors, then proper transistor operation is achieved, but the well boundary requires a large gap, increasing the arrangement region and chip size
Solution Approach 1:
The patent merges the N-type well and P-type well into a single shared well structure. The clamping PMOS transistors and power-supply interruption NMOS transistors share a common well region, eliminating the need for separate wells and the large gap boundaries between them. This merging reduces the arrangement region and chip size while maintaining proper transistor operation through appropriate well doping and potential control.
3Loss of energy
If power-supply interruption switches are used to interrupt ground potential application, then leakage current is reduced in standby mode, but the switches and clamping transistors require separate wells, increasing the arrangement region
Solution Approach 1:
The patent combines the power-supply interruption NMOS transistors and clamping PMOS transistors into a shared well structure. This merging eliminates the need for separate N-type and P-type wells with their large boundary gaps, thereby reducing the arrangement region and device complexity while maintaining the ability to control leakage current through coordinated operation of the switches and clamping transistors.
Data Source
AI summary
A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a ground potential line, when the memory cells are in an operation mode, a first P-type MIS transistor connected between the source potential line and the ground potential line, and fixing the source potential when the memory cells are in the sleep mode, and a bias generation circuit provided in a peripheral circuit area, and supplying a first bias potential to the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.