SRAM Leakage Control via Dynamic Voltage Adjustment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In deep submicron technology, static random access memory (SRAM) experiences increased leakage current, leading to a reduction in operating voltage and read margin, which affects its performance in high-speed, low-power applications.

Innovation Solution

The SRAM design incorporates a column driver, row driver, and control unit to selectively adjust the voltage of memory cells between a first and second preset value, reducing leakage current by managing the voltage in normal and stand-by modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the operating voltage is reduced to handle larger leakage current, then the leakage current problem is temporarily masked, but the read margin is reduced

Engineering Contradiction:
Improveleakage current controlVSAvoidread margin
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent applies dynamics by making the voltage of the second electrode dynamic rather than fixed. A control unit adjusts the voltage of the second electrode between a first voltage (higher than ground) in stand-by mode to reduce leakage current, and a second voltage (ground voltage) in normal mode to ensure proper read/write operations. This dynamic voltage adjustment resolves the contradiction between controlling leakage current and maintaining read margin.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter of the second electrode based on operational mode. By switching the voltage between two discrete values (first voltage > ground, second voltage = ground) depending on whether the memory is in stand-by or normal operation mode, the system optimizes both leakage current control and read margin performance without compromising either parameter permanently.

Inventive Principle:
Principle #35Parameter changes

2Speed

If conventional SRAM design is used in deep submicron technology, then high speed operation is achieved, but leakage current increases significantly

Engineering Contradiction:
Improveoperating speedVSAvoidleakage current
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent implements periodic action by switching the voltage of the second electrode between two states based on operational requirements. In stand-by mode, the higher first voltage is applied periodically to minimize leakage current. During active read/write operations, the voltage switches to the second voltage (ground) to enable proper signal levels. This periodic voltage switching reduces overall energy loss while maintaining high-speed operation capability.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7755925B2Static random access memory
Publication Date: 2010.07.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US7755925B2 patent drawing
  • US7755925B2 patent drawing
  • US7755925B2 patent drawing

AI summary

A static random access memory comprising a column driver, a row driver, a cell, and a control unit is disclosed. The column driver selects a first word line or a second word line. The row provides data to a first bit line and a second bit line. The data of the first bit line is opposite to that of the second bit line. The control unit controls the voltage of the cell. In normal mode, the voltage of the cell is equal to a second voltage. In stand-by mode, the voltage of the cell exceeds the second voltage.