Current Limiter Circuit for SRAM Sleep-Mode Leakage Control
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Solution Overview
Problem
In System-on-chip (SoC) and microcontroller systems, high power consumption and current leakage during sleep or low-power modes pose challenges, particularly due to data retention requirements, which can lead to regulator malfunction and data loss, especially at higher temperatures.
Innovation Solution
A dual voltage dropping element/current sensor circuit is implemented to reduce power availability to the load by establishing a temperature-dependent voltage drop, and a current limiter circuit disconnects the power supply when excessive current is drawn, thereby controlling current leakage and maintaining regulator integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data retention is maintained in SRAM memory during sleep mode, then awakening response time is reduced, but power consumption and current leakage increase significantly
Solution Approach 1:
The SRAM memory is divided into multiple banks, and the power supply is segmented accordingly. During sleep mode, only necessary SRAM banks remain powered while others are disconnected, reducing overall power consumption while maintaining data retention in active banks and enabling fast awakening.
Solution Approach 2:
The power supply configuration is made dynamic through switchable connections that can adapt between active and sleep modes. The circuit automatically adjusts power distribution to SRAM banks based on operational requirements, optimizing the balance between data retention, response time, and power consumption.
2Loss of time
If data retention is maintained in SRAM memory during sleep mode, then awakening response time is reduced, but current leakage increases and may cause regulator malfunction
Solution Approach 1:
The circuit incorporates current sensing that monitors current leakage from SRAM banks during sleep mode. When the sensed current exceeds a predetermined threshold, the feedback mechanism automatically disconnects the power supply from affected SRAM banks, preventing regulator malfunction while preserving data in safely powered banks.
Solution Approach 2:
Switchable connections act as intermediary elements between the power supply and SRAM banks. These intermediaries enable controlled disconnection of individual banks when current leakage becomes problematic, protecting the regulator while maintaining power to banks that require data retention.
3Use of energy by moving object
If voltage is reduced to limit current leakage, then power consumption decreases, but data retention capability deteriorates
Solution Approach 1:
The power supply voltage is segmented and applied selectively to different SRAM banks. During sleep mode, necessary banks receive sufficient voltage to maintain data retention, while other banks are completely disconnected. This segmentation allows the system to achieve low power consumption without compromising data retention in active banks.
Data Source
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AI summary
Methods, systems and circuits for controlling the power available to the load, by reducing the power available to the load, and additionally or alternatively, limiting the current available by pre-establishing a maximum reference current. The reference current is compared to the actual or estimated current drawn by the load or part of the load. The comparison result is used to control a device or switch (M6) which disconnects the power supply or power supply regulator, whether connected directly to the load or connected via voltage dropping device M3), to one or more of a plurality of the load blocks when the maximum current is exceeded.