SRAM Memory Cell With Low Potential Switching for Leakage Reduction
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Solution Overview
Problem
Conventional SRAM cells with six transistors face instability and data corruption when scaled down and operated at low voltage, and SRAM cells with eight transistors increase cell area and signal lines, leading to inefficiencies in data storage and retrieval.
Innovation Solution
A semiconductor memory device with a memory cell comprising seven transistors, including a holding control transistor, that switches the low power source potential between the inverter circuits to prevent data corruption, reduce leakage current, and enhance operational margins during reading and writing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of transistors is made shorter to improve speed, then the operating speed is improved, but the static noise margin is decreased and data corruption occurs
Solution Approach 1:
The patent applies dynamics by making the low power source potential switchable between a first level (during read operations) and a second level (during write and hold operations). This dynamic adjustment of the power source potential stabilizes the drive transistor characteristics during read operations, preventing data corruption while maintaining high-speed operation with shorter channel lengths.
Solution Approach 2:
The patent changes the parameter of power source potential by switching it between two different levels based on the operation mode. During read operations, the low power source potential is switched to the first level to enhance drive transistor stability and prevent data corruption, while during write and hold operations, it is switched to the second level to maintain normal operation. This parameter change resolves the contradiction between speed and reliability.
2Reliability
If an SRAM cell with eight transistors is used to prevent data corruption, then data stability is improved, but the cell area and number of signal lines increase
Solution Approach 1:
The patent extracts the essential function of preventing data corruption from the complex eight-transistor structure and implements it in a simplified manner by adding only one transistor (the holding control transistor) to the conventional six-transistor SRAM cell. This selective extraction and simplification achieves data stability while minimizing the increase in cell area.
Solution Approach 2:
The holding control transistor serves multiple functions: it controls the switching of the low power source potential, stabilizes the drive transistor during read operations, and prevents data corruption. This multi-functionality allows the patent to achieve data stability with minimal additional circuitry, avoiding the need for an eight-transistor structure.
3Reliability
If the low power source potential is switched to prevent data corruption, then data stability is improved, but leakage current increases
Solution Approach 1:
The patent applies periodic action by switching the low power source potential only during specific read operations when needed, rather than maintaining it continuously. The potential is switched to the first level during read operations to prevent data corruption, then switched back to the second level during write and hold operations to reduce leakage current. This periodic switching resolves the contradiction between data stability and energy loss.
Data Source
AI summary
In a reading operation, an off time and a reading time of a holding control transistor is controlled by a replica circuit, so that a read margin is enlarged. Furthermore, a high power source potential and a low power source potential of an SRAM memory cell are switched in reading and writing operations of the memory cell and in a data holding state by a power source potential switching portion. As a result, a write margin is enlarged, and a leakage current is reduced.