Intermediate-Voltage SRAM Level Shifter for Low-Power Wide Voltage Gaps
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Solution Overview
Problem
Dual rail SRAM architectures face challenges in reducing memory access time while maintaining low leakage power, and as the voltage difference between high and low voltage domains increases, leakage and noise also rise, necessitating a level shifter that can achieve a wide range of voltages with low energy dissipation.
Innovation Solution
A low voltage level shifter is designed with multiplexers that selectively apply an intermediate voltage (Vm) to PMOS transistor gates, reducing current and power dissipation by 43% and supporting a 500 mV voltage separation between power supply levels, compared to previous level shifters which only supported up to 350 mV.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the voltage difference between high voltage domain and low voltage domain is increased to reduce memory leakage power, then leakage power is reduced significantly, but noise increases and memory access time increases
Solution Approach 1:
The patent introduces an intermediate voltage domain (Vddm) that acts as a mediator between the low voltage logic domain (Vdd) and the high voltage memory array domain. This intermediate domain enables faster memory access by allowing level-shifting operations to occur at a voltage level closer to the high voltage domain, reducing the time penalty associated with large voltage differences while maintaining the leakage power benefits of the dual-rail architecture.
Solution Approach 2:
The patent segments the voltage domains into three distinct levels: low voltage (Vdd) for logic operations, intermediate voltage (Vddm) for level shifting, and high voltage for memory array operations. This segmentation allows each domain to be optimized independently, with the intermediate domain serving as a buffer that reduces the impact of large voltage differences on access time.
2Loss of energy
If the voltage difference between power supply levels is increased to reduce leakage power, then leakage power is reduced, but energy dissipation in level shifter increases
Solution Approach 1:
The patent employs dynamic control of the level shifter circuitry, where the intermediate voltage domain (Vddm) is selectively activated based on the operating conditions. The level shifter uses controlled switches and transistors that dynamically adjust their operation to minimize energy dissipation during voltage level transitions, especially when operating across large voltage differences.
Solution Approach 2:
The patent changes the voltage parameter by introducing an intermediate voltage level (Vddm) that is dynamically adjusted based on the difference between Vdd and the high voltage domain. This parameter change allows the level shifter to operate more efficiently by reducing the voltage swing required during level shifting operations, thereby reducing energy dissipation.
3Adaptability or versatility
If conventional level shifter is used with large voltage separation, then it cannot support the voltage range, but adding support for larger voltage separation increases device complexity
Solution Approach 1:
The patent designs the level shifter circuit to serve multiple voltage level transitions simultaneously. The intermediate voltage domain (Vddm) and the associated level shifting circuitry are configured to handle transitions between Vdd-Vddm, Vddm-high voltage, and potentially direct Vdd-high voltage transitions. This multi-functional design allows the same circuit structure to support a wide range of voltage separations without proportionally increasing complexity.
Data Source
AI summary
A voltage level shifter for an SRAM device includes a level shifter input and provides a second voltage level. A voltage input terminal receives a first signal at a first voltage level and an inverter having an input and an output with the voltage input terminal is connected to the inverter input. A first voltage selector selectively applies an intermediate voltage to the gate of a PMOS transistor in a first complementary pair when the voltage of a complementary level shift output voltage rises to a logical 1 and a second voltage selector applies the intermediate voltage to the gate of a PMOS transistor in a second complementary pair when the voltage of the level shift output voltage node rises to a logical 1. The PMOS transistor current is thereby reduced resulting in lower energy dissipation and supporting a larger voltage separation between the first and second voltage levels.