Local Sense Feedback Circuit for SRAM Power Reduction
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Solution Overview
Problem
Existing SRAM arrays face challenges in reducing operating power consumption, particularly during read and write-back operations, due to the need for global sense amplifiers and bit line driving, which increases power requirements and array area usage.
Innovation Solution
The integration of local sense and feedback circuits within SRAM arrays, allowing for local sensing and rewriting of memory states without the need for full global read and write-back operations, thereby reducing power consumption by utilizing separate local bit lines for sensing and feedback.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If global read and write-back operations are used to preserve half-addressed cells during write cycles, then memory state integrity is maintained, but power consumption increases significantly
Solution Approach 1:
The patent divides the SRAM array into multiple blocks, each with its own local sense and feedback circuitry. This segmentation allows only the specific block containing the targeted cell to be accessed during write operations, while other blocks remain in high-impedance state, significantly reducing the number of activated sense amplifiers and bit lines, thereby reducing power consumption while maintaining the integrity of half-addressed cells through localized feedback.
Solution Approach 2:
The patent implements local sense and feedback circuits at the block level rather than using global sense amplifiers for the entire array. This local quality approach enables precise control of sensing and feedback operations to only where needed (specific blocks), avoiding the activation of unnecessary global bit lines and sense amplifiers, thus reducing power consumption while preserving memory state integrity in half-addressed cells.
2Measurement precision
If global sense amplifiers are used for reading SRAM cells, then accurate memory state detection is achieved, but array area usage increases
Solution Approach 1:
The patent segments the SRAM array into multiple blocks with dedicated local sense circuits for each block. This segmentation reduces the area required per block compared to a monolithic global sense amplifier approach, as each local sense circuit only needs to service its specific block rather than the entire array. The segmented architecture achieves accurate memory state detection within each block while reducing overall array area utilization.
Solution Approach 2:
The patent introduces a hierarchical dimension to the SRAM architecture by organizing it into blocks with local sense circuits, creating a two-level structure (block level and array level). This dimensional organization allows local sense circuits to handle fine-grained sensing tasks within blocks, reducing the burden on global sense amplifiers and optimizing the area-efficiency trade-off by distributing sensing functionality across multiple localized units rather than relying on a single global unit.
Data Source
AI summary
An integrated circuit having an SRAM array includes SRAM cells arranged in rows and columns, and a global read circuit connected to globally read SRAM cells corresponding to accessed rows and columns of the SRAM array. The SRAM array also includes a separate, local sense and feedback circuit connected to a local column of the SRAM array, wherein a sensing portion indicates a memory state of an SRAM cell in an accessed row of the local column and a feedback portion rewrites the memory state back into the SRAM cell. Additionally, a method of operating an integrated circuit having an SRAM array includes providing an SRAM cell in an addressed condition of the SRAM array. The method also includes locally sensing a current memory state of the SRAM cell and locally feeding back to the SRAM cell to retain the memory state during the addressed condition.