In-Memory SRAM Logic and Copy Operations to Cut Data Transfer Latency
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Solution Overview
Problem
SRAM memory devices face challenges in performing operations within the device itself, leading to performance latency and increased complexity due to the need to send data outside the device for processing, which incurs additional time and resource usage.
Innovation Solution
The SRAM circuitry is modified to enable data processing and writing within the device, allowing for toggle and copy operations, as well as logic operations like AND, OR, and majority functions, by using control memory cells and concurrently active word lines to develop bit line voltages for sense amplifier outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is sent outside the SRAM device for processing, then operations can be performed, but performance latency increases and execution time is extended
Solution Approach 1:
The patent merges storage and processing functions by integrating logic operation circuits directly within the SRAM device structure. Memory cells are configured to perform logic operations (AND, OR, majority functions) internally without requiring data to be transferred to external processing units, thereby eliminating transfer latency and improving execution speed
Solution Approach 2:
The SRAM device is segmented into multiple functional blocks including memory cell arrays and dedicated logic operation circuits. Each block can independently perform specific operations, allowing parallel processing and reducing overall execution time for complex operations
2Productivity
If data is sent outside the SRAM device for processing, then operations can be completed, but device complexity and resource usage increase
Solution Approach 1:
The logic operation circuits are designed with multi-functionality, where the same circuit structures can perform multiple logic operations (AND, OR, majority functions) by configuring control signals. This universal approach increases processing capability without proportionally increasing device complexity
Solution Approach 2:
The SRAM device is enhanced with self-service capabilities where memory cells can perform logic operations on stored data independently. The device serves its own processing needs through integrated logic circuits, reducing reliance on external processing resources and simplifying the overall system architecture
Data Source
AI summary
Embodiments herein relate to circuitry which allows data to be processed and written back within an SRAM device. In a toggle operation, a memory cell is read and the bit at the complementary output node of a sense amplifier is written back to the memory cell. In a copy operation, a memory cell is read and the bit at the primary output node of the sense amplifier is written to another memory cell in the column. In another aspect, logic operations such as AND, OR, majority, AND-OR, OR-AND, and associated inverse operations can be performed within the SRAM device. This can involve writing data to one or more control memory cells in the same column as the data memory cells involved in the logic operation, and setting the respective word lines to be active concurrently.