SRAM Logic Semiconductor Gate Impurity Diffusion Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face challenges in securing transistor characteristics of SRAM section n-type and p-type MIS transistors without increasing the width of element isolation between them, while also improving logic circuit section transistor characteristics, due to issues with impurity concentration and diffusion rates affecting gate insulating film reliability and threshold voltage control.
Innovation Solution
The semiconductor device and manufacturing method involve forming n-type and p-type gate electrodes with specific impurity concentrations and diffusion profiles, where the n-type gate electrode in the SRAM section has a lower impurity concentration than the logic circuit section, preventing excessive diffusion and maintaining transistor characteristics without widening the element isolation, and increasing impurity concentrations in the logic circuit section for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the width of element isolation region is reduced to miniaturize the semiconductor device, then the area of SRAM cells is reduced, but the transistor characteristics of n-type and p-type MIS transistors cannot be secured due to excessive impurity diffusion
Solution Approach 1:
The patent applies local quality by differentiating impurity concentration levels between SRAM section gate electrodes and logic circuit section gate electrodes. Specifically, the SRAM section n-type gate electrode has a first impurity concentration while the logic circuit section n-type gate electrode has a second impurity concentration higher than the first. This localized differentiation allows the SRAM section to maintain proper transistor characteristics with lower impurity diffusion even with reduced element isolation width, while the logic circuit section achieves improved transistor characteristics through higher impurity concentrations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach secures transistor characteristics in the SRAM section without increasing element isolation width, reduces the area of SRAM cells, and enhances the performance of logic circuit section transistors by optimizing impurity concentrations and diffusion boundaries.
Implementation Method 1
thermal treatment is performed after implantation of the conductive impurity for promoting mutual diffusion of an n-type impurity in the n-type gate electrode and a p-type impurity in the p-type electrode in the integrally-formed n-type and p-type gate electrodes
Data Source
AI summary
A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.