SRAM-Logic Cell Layout Unification for Higher Chip Density
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Solution Overview
Problem
The existing layout topology of SRAM cells and standard logic cells on semiconductor chips results in inefficient area utilization due to their different sizes and the need for isolation structures, limiting the integration and spacing between these cells.
Innovation Solution
The SRAM cell and logic cell are designed with similar layout topologies, allowing them to be physically connected and eliminating the need for isolation structures, with active structures extending through both cells and being connected to a signal line and ground line, thereby optimizing area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM cells and standard logic cells are disposed in different regions with isolation structures, then device reliability is improved, but area utilization efficiency deteriorates
Solution Approach 1:
The patent merges the layout topologies of SRAM cells and logic cells by designing the SRAM cell with the same structure as the logic cell (including identical active structures, gate lines, and contact arrangements). This unification eliminates the need for isolation structures between different cell types, allowing them to be densely packed together while maintaining device reliability through consistent design rules and fabrication processes.
Solution Approach 2:
The patent creates a universal cell design where the same basic structure serves both as SRAM cell and logic cell. By making the layouts identical and using the same active structures (first and second active structures with complementary conductive types), the design achieves multi-functionality where the fundamental building block can be configured for different purposes without requiring separate isolation regions.
2Reliability
If SRAM cell height is made much greater than logic cell height, then SRAM cell functionality is improved, but area utilization efficiency deteriorates
Solution Approach 1:
The patent changes the parameter of cell height by designing the SRAM cell to have the same height as the logic cell. This is achieved by configuring the number and arrangement of transistors and active structures to match the logic cell dimensions, thereby enabling uniform cell heights that improve area utilization while maintaining SRAM functionality through optimized transistor configurations within the constrained height.
3Reliability
If isolation structures and dummy SRAM cells are added between SRAM and logic cells, then device reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the isolation structures and dummy SRAM cells from the design. By eliminating these additional components through unified layout topology, the device complexity is reduced while reliability is maintained through consistent design rules applied to all cells. The removal of isolation structures simplifies the fabrication process and reduces the total number of components that need to be manufactured and tested.
Data Source
AI summary
A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.