SRAM Macro Layout With Backside Routing for Stacked Transistors
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Solution Overview
Problem
Current standard cell designs face challenges in providing adequate access and routing for both control signals and power signals to stacked transistors due to design and manufacturing constraints, particularly when limited to topside routing, leading to insufficient paths without expanding the cell size.
Innovation Solution
Implementing both topside and backside metal layers for routing connections to stacked transistors, allowing for efficient connections and power signals within standard cells, including heterogeneous or homogeneous transistors, without increasing the cell's size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If only topside metal layers are used for routing connections to stacked transistors, then the routing complexity is reduced, but the number of available paths for control signals and power signals becomes insufficient
Solution Approach 1:
The patent utilizes both topside and backside metal layers to provide routing paths, effectively adding a vertical dimension to the routing architecture. This allows control signals and power signals to be routed through multiple layers, increasing the number of available paths without significantly increasing the planar footprint of the standard cell.
2Adaptability or versatility
If the cell size is increased to provide more routing paths, then the number of available paths increases, but the cell area becomes larger
Solution Approach 1:
By utilizing the vertical dimension through backside metal layers, the patent provides additional routing paths within the same planar cell area. This eliminates the need to increase cell area to accommodate more routing paths, as the third dimension (vertical layering) is exploited instead.
Solution Approach 2:
The routing function is segmented across multiple metal layers (topside and backside), allowing different signals to be routed through different layers. This segmentation enables multiple paths to coexist within the same cell area by distributing routing responsibilities across vertical layers.
3Productivity
If standard cell size is reduced to increase circuit density, then the circuit density increases, but the access to components within the standard cells becomes more difficult
Solution Approach 1:
The patent maintains small standard cell dimensions by utilizing backside metal layers for routing. This vertical routing approach allows adequate access to stacked transistors and other components without increasing the planar cell size, thereby maintaining high circuit density while ensuring proper component accessibility.
Data Source
AI summary
A memory device layout that implements SRAM cells with stacked transistors is disclosed. The memory utilizes both topside metal routing and backside metal routing for routing of bitlines between bit cells with stacked transistors and logic cells coupled to the bit cells.