SRAM Macro Layout With Dual-Side Routing for Stacked Transistors
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Solution Overview
Problem
Current standard cell designs face challenges in providing adequate access and routing for both topside and backside connections to stacked transistors, especially when reducing cell size and increasing complexity, leading to manufacturing and design constraints.
Innovation Solution
Implementing routing in both topside and backside metal layers to facilitate connections for control signals and power signals in stacked transistors within standard cells, allowing for compact designs that adhere to current manufacturing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If standard cell size is reduced to increase circuit density, then productivity and device complexity are improved, but ease of manufacture and accessibility to components deteriorate
Solution Approach 1:
The patent introduces a third vertical dimension by stacking transistors on top of each other rather than arranging them horizontally in the traditional planar layout. This vertical stacking allows standard cells to maintain smaller footprints while preserving manufacturing accessibility, as each transistor in the stack can still be individually accessed through the substrate from the backside.
2Ease of manufacture
If only topside routing is used for control signals and backside routing for power signals, then manufacturing constraints are maintained, but device complexity and routing limitations increase
Solution Approach 1:
The patent makes the substrate bidirectional, allowing both control signals and power signals to be routed from both the topside and backside. This multi-functional routing capability enables flexible signal distribution to stacked transistors while maintaining compatibility with existing manufacturing processes that use separate topside and backside routing layers.
Data Source
AI summary
A memory device layout that implements SRAM cells with stacked transistors is disclosed. The memory utilizes both topside metal routing and backside metal routing for routing of bitlines between bit cells with stacked transistors and logic cells coupled to the bit cells.