SRAM Macro Sparing for Yield Improvement in Computer Chips
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Solution Overview
Problem
Computer chips with embedded SRAM macros face yield loss and field failures due to defects, as redundancy within SRAM macros becomes insufficient with increasing chip complexity, rendering entire chips unusable or degraded.
Innovation Solution
Implementing SRAM macro sparing, where controls and data flow for a single macro are rerouted to spare macros, allowing a defective macro to be shut off and replaced, thereby increasing manufacturing yield and reducing field replacement rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy is added within SRAM macros in the form of spare bit rows and columns, then manufacturing yield increases, but the effectiveness diminishes as the percentage of area devoted to embedded SRAM increases
Solution Approach 1:
The chip is divided into multiple SRAM macro groups, with each group containing a designated spare macro. This segmentation allows independent redundancy management at the group level rather than requiring full-chip redundancy, resolving the contradiction between improving yield and limiting area complexity.
Solution Approach 2:
The invention introduces a hierarchical redundancy structure with two dimensions: intra-macro redundancy (spare bit rows/columns) and inter-macro redundancy (spare macros at the group level). This multi-dimensional approach to redundancy resolves the contradiction by providing backup at multiple levels without proportionally increasing overall chip area.
2Adaptability or versatility
If the number of SRAM macros on a single chip increases, then chip functionality improves, but the likelihood of a single macro depleting all built-in redundancy increases
Solution Approach 1:
The chip is divided into multiple SRAM macro groups, with each group containing a designated spare macro. This segmentation allows independent redundancy management at the group level rather than requiring full-chip redundancy, resolving the contradiction between improving yield and limiting area complexity.
Solution Approach 2:
Spare macros act as intermediary backup elements that can be activated when defects are detected in operational macros. The sparing mechanism includes control logic that mediates between the defective macro and the spare macro, enabling seamless replacement and maintaining chip functionality.
3Reliability
If local defects affect multiple elements of a single macro, then chip usability is degraded, but without another layer of redundancy the loss of a single SRAM macro renders an entire chip unusable or degraded
Solution Approach 1:
The chip is divided into multiple SRAM macro groups, with each group containing a designated spare macro. This segmentation allows independent redundancy management at the group level rather than requiring full-chip redundancy, resolving the contradiction between improving yield and limiting area complexity.
Solution Approach 2:
The invention implements beforehand cushioning by providing spare macros in advance that can compensate for local defects affecting multiple elements. The spare macros are prepared beforehand and can be activated when defects occur, cushioning against the impact of local failures without requiring complex real-time repair mechanisms.
Data Source
AI summary
SRAM macro sparing allows for full chip function despite the loss of one or more SRAM macros. The controls and data flow for any single macro within a protected group are made available to the spare or spares for that group. This allows a defective or failed SRAM macro to be shut off and replaced by a spare macro, dramatically increasing manufacturing yield and decreasing field replacement rates. The larger the protected group, the fewer the number of spares required for similar improvements in yield, but also the more difficult the task of making all the controls and dataflow available to the spare(s). In the case of the Level 2 Cache chip for the planned IBM Z6 computer, there are 4 protected groups with 192 SRAM macros per group. Each protected group is supplanted with an additional 2 spare SRAM macros, along with sparing controls and dataflow that allow either spare to replace any of the 192 protected SRAM macros.