SRAM Compute-in-Memory Circuit for In-Memory Convolution
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Solution Overview
Problem
Current artificial neural networks face inefficiencies in convolution computations, particularly in memory usage and processing power, which hinders their performance in applications like pattern recognition and classification.
Innovation Solution
The implementation of a circuit and method for in-memory convolution computation using a memory cell with a bit-line and complementary bit-line, coupled with a computation circuit comprising a counter, NMOS, and PMOS transistors, enables logical operations within the memory cell, optimizing computation by reducing the need for external processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If convolution computations are performed using traditional neural network architectures with separate processing nodes, then computational flexibility is maintained, but memory usage and processing power requirements increase significantly
Solution Approach 1:
The patent merges memory storage and computation functions into a unified structure by integrating computation circuits directly within the memory array. Memory cells store weights while associated computation circuits perform convolution operations on stored data, eliminating the need for separate processing nodes and reducing data movement between memory and processor units.
Solution Approach 2:
The memory cells are designed to serve dual purposes: storing weight parameters and performing computation operations. The same memory infrastructure that holds data is also used to execute convolution computations, making the memory system multi-functional and reducing overall system resource requirements.
2Productivity
If convolution computations are performed using traditional neural network architectures with separate processing nodes, then computational operations can be executed, but power consumption increases due to data movement
Solution Approach 1:
By combining memory and computation units into integrated memory computation elements, the patent eliminates data movement between separate memory and processing components. Computation operations are performed in-place within the memory array, significantly reducing the energy associated with data transfer and improving processing efficiency.
3Ease of operation
If external processing is used for convolution operations, then computational tasks can be completed, but the system requires more external processing power and memory bandwidth
Solution Approach 1:
The memory system performs computation operations autonomously using integrated computation circuits within the memory array. Weight values stored in memory cells are directly utilized by associated computation circuits to perform convolution operations, eliminating the need for external processing units and reducing system complexity.
Data Source
AI summary
Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.